Design of MoS2 NCFET Featuring Subthermodynamic Limit SS, No More Than 5 mV/V DIBR, and 0.8% Threshold Voltage Variation at 10-nm Channel Length: Modeling and Analysis
{"title":"Design of MoS2 NCFET Featuring Subthermodynamic Limit SS, No More Than 5 mV/V DIBR, and 0.8% Threshold Voltage Variation at 10-nm Channel Length: Modeling and Analysis","authors":"Sanket Mitra;Chandrima Mondal;Abhijit Biswas","doi":"10.1109/TED.2025.3529407","DOIUrl":null,"url":null,"abstract":"In this work, we present a design, model, and analysis for a multilayered transition metal dichalcogenide (TMD)-based negative capacitance (NC) FET that achieves a subthreshold swing (SS) well below the thermodynamic limit, a maximum drain-induced barrier rise (DIBR) of 5 mV/V, and a threshold voltage (<inline-formula> <tex-math>${V} _{\\text {th}}$ </tex-math></inline-formula>) roll-up confined within 0.8% at a 10-nm channel length, using hafnium zirconium oxide (Hf0.5Zr0.5O2) as the ferroelectric material. Various parameters are considered, including ferroelectric layer thickness (<inline-formula> <tex-math>${t} _{\\text {FE}}$ </tex-math></inline-formula>), coercive electric field (<inline-formula> <tex-math>${E} _{c}$ </tex-math></inline-formula>), remanent polarization (<inline-formula> <tex-math>${P} _{r}$ </tex-math></inline-formula>), number of molybdenum disulfide (MoS2) layers (N), equivalent front and buried oxide thicknesses (EOT<inline-formula> <tex-math>$_{\\mathbf {f}}$ </tex-math></inline-formula>, EOTb), channel length (L), and drain-source bias (<inline-formula> <tex-math>${V} _{\\text {DS}}$ </tex-math></inline-formula>). A surface-potential-based model, accounting for interfacial traps, is employed to compute performance parameters such as <inline-formula> <tex-math>${V}_{\\text {th}}$ </tex-math></inline-formula>, SS, and DIBR. The model is validated against simulation results and existing data. The capacitance matching is performed to ensure hysteresis-free and stable NC operation. Conditions for the ferroelectric parameters (<inline-formula> <tex-math>$\\alpha $ </tex-math></inline-formula>) and <inline-formula> <tex-math>${t}_{\\text {FE}}$ </tex-math></inline-formula> are derived to mitigate short-channel effects (SCEs). Optimization is carried out to achieve subthermodynamic SS while maintaining 5 mV/V DIBR and a <inline-formula> <tex-math>${V}_{\\text {th}}$ </tex-math></inline-formula> roll-up below 0.8%, with values recorded for various combinations of N, EOTf, EOTb, and <inline-formula> <tex-math>${V}_{\\text {DS}}$ </tex-math></inline-formula>. Unlike direct bandgap monolayer MoS2, multilayer MoS2, an indirect bandgap semiconductor, is preferred due to its lower interface-trapped charge density and augmented performance. The feasibility of the recorded <inline-formula> <tex-math>$\\alpha ~{t}_{\\text {FE}}$ </tex-math></inline-formula> values is verified against experimental results, and an empirical model is proposed to guide the selection of ferroelectric materials for specific <inline-formula> <tex-math>${t}_{\\text {FE}}$ </tex-math></inline-formula>.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1476-1482"},"PeriodicalIF":2.9000,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Electron Devices","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10852540/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
In this work, we present a design, model, and analysis for a multilayered transition metal dichalcogenide (TMD)-based negative capacitance (NC) FET that achieves a subthreshold swing (SS) well below the thermodynamic limit, a maximum drain-induced barrier rise (DIBR) of 5 mV/V, and a threshold voltage (${V} _{\text {th}}$ ) roll-up confined within 0.8% at a 10-nm channel length, using hafnium zirconium oxide (Hf0.5Zr0.5O2) as the ferroelectric material. Various parameters are considered, including ferroelectric layer thickness (${t} _{\text {FE}}$ ), coercive electric field (${E} _{c}$ ), remanent polarization (${P} _{r}$ ), number of molybdenum disulfide (MoS2) layers (N), equivalent front and buried oxide thicknesses (EOT$_{\mathbf {f}}$ , EOTb), channel length (L), and drain-source bias (${V} _{\text {DS}}$ ). A surface-potential-based model, accounting for interfacial traps, is employed to compute performance parameters such as ${V}_{\text {th}}$ , SS, and DIBR. The model is validated against simulation results and existing data. The capacitance matching is performed to ensure hysteresis-free and stable NC operation. Conditions for the ferroelectric parameters ($\alpha $ ) and ${t}_{\text {FE}}$ are derived to mitigate short-channel effects (SCEs). Optimization is carried out to achieve subthermodynamic SS while maintaining 5 mV/V DIBR and a ${V}_{\text {th}}$ roll-up below 0.8%, with values recorded for various combinations of N, EOTf, EOTb, and ${V}_{\text {DS}}$ . Unlike direct bandgap monolayer MoS2, multilayer MoS2, an indirect bandgap semiconductor, is preferred due to its lower interface-trapped charge density and augmented performance. The feasibility of the recorded $\alpha ~{t}_{\text {FE}}$ values is verified against experimental results, and an empirical model is proposed to guide the selection of ferroelectric materials for specific ${t}_{\text {FE}}$ .
期刊介绍:
IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.