Balancing I/O and wear-out distribution inside SSDs with optimized cache management

Abstract

NAND flash memory-based solid-state drives (SSDs) have been adopted as storage infrastructure in a wide range of computing systems. In order to service an I/O request, the logical page address (LPA) of the request should be mapped to a physical page address (PPA), termed page-level address mapping in SSDs. As a fundamental mapping scheme, static mapping needs a small-scale mapping table and ensures good read parallelism, but it may bring about uneven I/O and wear-out distribution across SSD parallel units (e.g. flash planes), thus resulting in low write efficiency. To mitigate the negative effects of static mapping, this paper proposes a novel cache management scheme to not only guarantee I/O responsiveness but also balance I/O and wear-out distribution. Specifically, we first introduce directly flushing a portion of data pages onto the flash array while they are cold and the target parallel units have endured a small number of erase operations. After that, we present a method for selecting victim data pages from the data cache, by referring to the factors of pending I/O requests and the wear-out level on the flash memory. Through a series of simulation experiments on selected block I/O traces of real-world applications, we show that our approach achieves an average I/O latency reduction of 16.1% compared to Baseline, 13.6% over GCaR, 12.4% over LCR, and 6.6% over ARB while simultaneously balancing I/O and wear-out distribution. These results demonstrate its superiority over existing state-of-the-art schemes.