Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET)

Abstract

This work assesses and analyzes negative-capacitance CFETs (NC-CFETs) with metal-ferroelectric-insulator-semiconductor (MFIS) and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) configurations through experimentally calibrated Landau-Khalatnikov model for an ultrathin (1.5 nm) single-crystalline HZO ferroelectric (FE). Results show a suppressed improvement with MFMIS topology over the MFIS topology in the subthreshold region if implemented with the CFET architecture due to the CFET-specific common-gate structure. We also propose an alternative MFMIS NC-CFET design with the FE stacked only at the top of the device (~5.3 times lower FE area compared to conventional MFMIS NC-CFET), which can significantly improve the capacitance matching and subthreshold swing provided an FE layer with relatively higher remnant polarization is used. In addition, a design guideline to optimize MFIS NC-CFET is also highlighted. Our study may provide insights into device design for future energy-efficient electronics.