Design and Testing of a 0.8-V Low-Voltage High-Rate Prototype Readout ASIC for the Micro-Pattern Gas Detector

Abstract

The micro-pattern gas detectors (MPGDs) offer high spatial and time resolution and a large active area, among which the micro-resistive WELL ( $\mu $ RWELL) detector has received increasing attention in recent years due to its simple structure, low material budget, and high counting rate capability. It is, therefore, proposed as an important option for the low-mass Inner TracKer (ITK) detector in the future Super Tau-Charm Facility (STCF). Considering the high luminosity in the STCF, the innermost ITK layer requires a new high-rate, low-noise, and low-power readout application-specific integrated circuit (ASIC). The first version of the prototype ASIC integrates a 32-channel analog processing circuit. In the charge-sensitive amplifier (CSA), the bulk-driven current mirror is adopted to reduce the headroom voltage and lower the supply voltage to 0.8 V, thereby reducing power consumption while maintaining the same channel thermal noise and transconductance. In addition, an equivalent “cold resistor” circuit is proposed to achieve both fast recovery and low noise. This ASIC has been fabricated in a 0.18- $\mu $ m CMOS process, and a series of tests has been performed. The equivalent noise charge (ENC) is measured to be 487 e $\mathrm {\mathbf {^{\text {-}}}}+29.2$ e $\mathrm {\mathbf {^{\text {-}}}}$ /pF with a charge measurement range of 40 fC and a peaking time of 25 ns. Meanwhile, the maximum repetition rate capability per channel at a 70-ns charge collection time is up to 4 MHz, while the power consumption is only 1.93 mW per channel, resulting in a figure of merit (FOM) of only 0.29 pJ.