MexSIC, a Data Acquisition Channel for SiPMs

Abstract

This work describes MexSIC, a data acquisition (DAQ) channel designed for silicon photomultipliers (SiPMs), composed of a mixed-mode application-specific integrated circuit (ASIC) front end, a field programmable gate array (FPGA)-based processing stage, and a user interface. The ASIC provides a 1-bit sigma-delta modulator ( $\Sigma \Delta -M$ ) digital equivalent of the input SiPM current, a flag indicating the start/end of the SiPM pulse, and a clock reference generated by an internal phase-locked loop (PLL). At the ASIC input stage, the SiPM current is converted to voltage by means of a 1.57-GHz bandwidth (BW) transimpedance amplifier (TIA), the gain of which can be switched between 21 and 48 dB, allowing for an input current range between $20~\mu $ A and 20 mA. The generated voltage signal is then fed to a trigger unit (TU) implemented to discriminate between desired signals and the spurious ones and, in parallel, also to a second-order $\Sigma \Delta $ modulator providing 6.1 effective number of bits (ENOB). The TU circuit sends a start/end bit flag by comparing the SiPM voltage signal with an 8-bit programmable voltage reference. $\Sigma \Delta $ was selected to have a single output line instead of using a data bus with many lines, which is important in applications where the number of SiPM channels being read out is very large. The 10-MHz BW $\Sigma \Delta -M$ uses an oversampling ratio (OSR) of 50 and a 1-GHz sampling clock that is generated by a PLL using an off-chip 100-MHz reference. The FPGA receives the ASIC $\Sigma \Delta $ modulated output signal and performs a decimation process by means of a cascade integrator comb (CIC) filter to complete the data recovery. The recovered signal is visualized in a MATLAB-programmed graphical user interface (GUI). The MexSIC ASIC was designed in a 180-nm CMOS standard process using Cadence software, and the processing stage was implemented in a Kintex-7 FPGA.