A 94.3-dB SNDR 184-dB FoMs 4th-Order Noise-Shaping SAR ADC With Dynamic-Amplifier-Assisted Cascaded Integrator

IF 2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Solid-State Circuits Letters Pub Date : 2025-02-21 DOI:10.1109/LSSC.2025.3544649

Kai-Cheng Cheng;Soon-Jyh Chang;Chung-Chieh Chen;Shuo-Hong Hung

引用次数: 0

Abstract

This letter presents a fully dynamic 4th-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with the proposed 4th-order cascaded integrator using dynamic-amplifier-assisted and passive integration. This ADC can achieve sharp NTF with only two dynamic amplifiers and is insensitive to process, voltage, and temperature (PVT) variation. The NS-SAR ADC occupies 0.09 mm2 in a 28-nm CMOS process. With a 1-V supply voltage, it consumes

$107.38~\mu $

W at 5 MS/s. The measured signal-to-noise and distortion ratio (SNDR) is 94.3 dB over a 100-kHz bandwidth (BW), resulting in a Schreier figure of merit (FoM) of 184 dB and a Walden FoM of 12.6 fJ/conv.-step.

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带动态放大器辅助级联积分器的94.3 db SNDR 184db fms四阶噪声整形SAR ADC

本文介绍了一种全动态四阶噪声整形（NS）逐次逼近寄存器（SAR）模数转换器（ADC），该转换器采用动态放大器辅助和无源集成的四阶级联积分器。该ADC仅使用两个动态放大器即可实现锐利的NTF，并且对工艺、电压和温度（PVT）变化不敏感。NS-SAR ADC采用28纳米CMOS工艺，占地0.09 mm2。在1 v电源电压下，在5 MS/s下功耗为107.38~\mu $ W。在100 khz带宽（BW）下，测量到的信噪比和失真比（SNDR）为94.3 dB，得到的Schreier优值图（FoM）为184 dB， Walden优值图（FoM）为12.6 fJ/ vs . step。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量