Comprehensive TCAD-Based Single Event Effect Study of TFET-Based 1T DRAM and Crossbar Memory Array

IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Device and Materials Reliability Pub Date : 2025-01-13 DOI:10.1109/TDMR.2025.3528903
Dhananjay Prakash;Neha Kamal;Avinash Lahgere
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Abstract

In this paper, a comprehensive TCAD-based single event effect (SEE) study on tunnel field effect transistor (TFET) based one transistor dynamic random access memory (1T DRAM) and crossbar memory array is demonstrated through well-calibrated 2-D TCAD simulations. The simulation study reveals that the regions near Gate 2 are more susceptible to SEE. In addition, in comparison to without SEE, when a high energy particle (HEP) strikes the device, the read “1” (R1) current remains the same, however, the read “0” (R0) current increases $\sim ~10\times $ at 358 K. As a result, the read current ratio (IR1/I $_{\mathrm {R0}}$ ) and the sense margin (SM) decreases. The IR1/IR0 ratio with SEE is found to be $\sim ~10^{2}$ , which is $10\times $ lower than ratio without SEE. In addition, the impact of various parameters such as linear energy transfer (LET), HEP strike time, HEP strike moment, and HEP radius on TFET-based 1T DRAM performance is also evaluated. Moreover, for a 2 x 2 crossbar memory array, the combination of SEE with word line disturbance mechanism causes $\sim ~10\times $ reduction in the R1 current at 358 K. Our findings will pave the way for further exploration and designing radiation-hardened TFET-based 1T DRAM for future low-power space applications.
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基于tfet的1T DRAM和横杆存储器阵列单事件效应综合研究
本文通过校准良好的二维TCAD仿真,对基于隧道场效应晶体管(TFET)的单晶体管动态随机存取存储器(1T DRAM)和交叉棒存储器阵列进行了全面的TCAD单事件效应(SEE)研究。仿真研究表明,靠近2号门的区域更容易受到SEE的影响。此外,与未使用SEE相比,当高能粒子(HEP)撞击器件时,读取的“1”(R1)电流保持不变,而读取的“0”(R0)电流在358k时增加了10倍。因此,读电流比(IR1/I $_{\mathrm {R0}}$)和感测余量(SM)减小。有SEE的IR1/IR0比值为$ $ sim ~10^{2}$,比没有SEE的IR1/IR0比值低$ $10 $ $。此外,还评估了线性能量传递(LET)、HEP打击时间、HEP打击力矩和HEP半径等参数对基于tfet的1T DRAM性能的影响。此外,对于2 × 2交叉棒存储器阵列,SEE与字线干扰机制的结合使R1电流在358k时降低了10倍。我们的研究结果将为进一步探索和设计基于tfet的抗辐射1T DRAM铺平道路,用于未来的低功耗空间应用。
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来源期刊
IEEE Transactions on Device and Materials Reliability
IEEE Transactions on Device and Materials Reliability 工程技术-工程:电子与电气
CiteScore
4.80
自引率
5.00%
发文量
71
审稿时长
6-12 weeks
期刊介绍: The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.
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