Morphological and strain engineering of SiGe cladded channels for stacked nanowire transistors

Abstract

This paper presents a comprehensive study of silicon germanium (SiGe) cladded channels for stacked nanowires (NWs), focusing on morphological control and strain engineering to enhance device performance. High-resolution transmission electron microscopy (TEM) was used to characterize the Si NWs and SiGe cladding morphology. The results demonstrate that the morphology of SiGe cladding can be controlled by adjusting the high-temperature H2 baking conditions, leading to shapes such as triangular, circular, and hexagonal. Technology computer-aided design simulations and geometric phase analysis of TEM images revealed that the maximum compressive stress of SiGe cladding is 3 GPa, corresponding to a compressive strain of 2.48%, which significantly enhances hole mobility. Electrical performance tests and simulations on p-type metal–oxide–semiconductor field-effect transistor devices with different morphologies showed excellent short-channel effect control, with a subthreshold swing (SS) of approximately 70 mV/dec and a drain-induced barrier lowering of only 40 mV/V. These findings provide valuable guidelines for fabricating high-quality SiGe channels with controlled structures, enabling the realization of high carrier mobilities in future devices.