Design and Hardware Implementation of Low-Latency 4-Splitting Tree-Structure-Based K-Means Clustering Trainer and Classifier Chip for Detecting Cybersecurity Attacks

Abstract

In this brief, we propose a first system chip architecture of 4-splitting tree-structure-based K-means clustering trainer and classifier. It mainly aims to efficiently detect cybersecurity attacks in the emerging AI-driven world. In addition, we also propose three design techniques to elaborate our chip, featuring a low-latency property in both training and classification aspects. Our developed architecture is first validated with the Xilinx FPGA platform. Furthermore, it is implemented in ASIC and well-verified with five representative cybersecurity-related datasets. The total core area with TSMC 40nm low-Vt CMOS technology only occupies 0.44 um2, maximally operating at 434.78 MHz and possessing a maximum classification throughput of 3.48 GBps on chip. In comparison, the speed-up ratio of training and classification is up to 9.33 and 8.73 times, respectively, successfully delivering a low-latency characteristic.