A 1.46-pJ/bit, 149-KF² RO TRNG Based on Reference-RO-Free Thresholding of Jitter Accumulation

Abstract

In this brief, a ring-oscillator-based true random number generator (RO-TRNG) is presented with an energy-efficient on-chip module for temporal thresholding of the accumulated jitter noise. The need of power-hungry reference ring oscillator (RO) for frequency collapse detection in previous implementation can be completely removed. In addition, by setting the RO-TRNG’s enable signal adaptively according to the output of the proposed jitter accumulation thresholding (JAT) module, the redundant oscillations in most cycles of the prior art can be fully eliminated, leading to significant energy saving per each TRNG bit. Based on a 65-nm 1.2 V standard CMOS process, the fabricated TRNG chips feature an ultra-compact silicon area of 149 K $F^{2}$ . Meanwhile, a high energy efficiency of 1.46 pJ/bit is achieved for the prototype chips operated under a supply voltage of 1.0 V and an overall throughput of 44.7 Mbps. High randomness of the fabricated TRNG chips is well validated by using both National Institute of Standards and Technology (NIST) and autocorrelation function (ACF) test tools. Moreover, high Shannon entropy values over 0.999998 are observed for the TRNG chips operated under an industrial temperature range of −40°C~125°C and a supply voltage range of 1.0 V~1.4 V, showing excellent tolerance to the process-voltage-temperature (PVT) variations.