Analysis and Characterization Approach of Variation Behavior for Dopant-Segregated Tunnel FETs With Self-Aligned Drain Underlap

Abstract

The novel dopant-segregated tunnel FET (DS-TFET) has recently been proposed and experimentally demonstrated as a promising low-power device on standard CMOS baseline platform. In this article, for high-volume production, we evaluate the variation behavior of DS-TFET and carefully study its physical mechanism. Different from conventional TFET, the doping gradient of tunnel junction (TDG) and the electrical length of drain underlap region ( ${L}_{\text {und}}$ ) are found to be the two dominant random variation sources, and the additional variation of ${L}_{\text {und}}$ results in the asymmetrical variation between $\sigma {I}$ on and $\sigma {I}$ off. Based on the measured and modeled I–V and C–V characteristics, a device-level characterization approach is further developed to electrically extract ${L}_{\text {und}}$ and the main variation sources, which is also verified through technology computer aided design (TCAD) simulation. The method of this work paves the way for the development of the variation-aware compact model and the DS-TFET-based circuit analysis, promoting the development of ultralow-power TFET-CMOS hybrid platform.