Da-Yeon Kim, Sang-Won Oh, Hyeon-Gi Hwang, Young-Seung Kim, Dong-Ryeol Oh
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引用次数: 0
Abstract
A 6-bit asynchronous loop-unrolled (LU) successive approximation register (SAR) analogue-to-digital converter (ADC) with a complementary voltage-to-time converter (CVTC) and the efficient latch technique needed for this structure are proposed. The proposed structure utilises CVTC to reduce the power consumed by the reset operation and halves the operating frequency of the CVTC. Designed with a 500-nm CMOS process, the 6-bit 10-MS/s LU SAR ADC shows a power saving of 23.66% compared to the VTC-based LU SAR ADC.
提出了一种具有互补电压-时间转换器（CVTC）的6位异步环展开（LU）逐次逼近寄存器（SAR）模数转换器（ADC）以及该结构所需的高效锁存技术。建议的结构利用CVTC来减少复位操作所消耗的功率，并将CVTC的工作频率减半。采用500纳米CMOS工艺设计的6位10 ms /s LU SAR ADC，与基于vtc的LU SAR ADC相比，功耗节省23.66%。
期刊介绍：
Electronics Letters is an internationally renowned peer-reviewed rapid-communication journal that publishes short original research papers every two weeks. Its broad and interdisciplinary scope covers the latest developments in all electronic engineering related fields including communication, biomedical, optical and device technologies. Electronics Letters also provides further insight into some of the latest developments through special features and interviews.
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As a journal at the forefront of its field, Electronics Letters publishes papers covering all themes of electronic and electrical engineering. The major themes of the journal are listed below.
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