Image encryption/decryption accelerator based on Fast Cosine Number Transform

IF 2.5 3区 工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Integration-The Vlsi Journal Pub Date : 2025-04-12 DOI:10.1016/j.vlsi.2025.102416
Zhiqiang Xu, Zhenmin Li, Feng Han, Xiaolei Wang, Gaoming Du
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Abstract

The Cosine Number Transform (CNT) and its Fast Cosine Number Transform (FCNT) are widely used in image encryption due to their modular arithmetic, which enhances computational accuracy. However, existing hardware architectures for FCNT suffer from long computation cycles and high resource consumption, making it challenging to meet the demands for fast image encryption. This paper proposes an eight-point FCNT hardware architecture with multiplier-less multiplication (MM), employing pipeline and time-division multiplexing methods. Based on this architecture, an image encryption hardware accelerator was implemented. Experimental results show that compared to existing methods, the proposed FCNT architecture reduces computational delay by 18.2%and decreases LUTs usage by 18.5% and FFs usage by 21.7%. Furthermore, compared to the current state-of-the-art, the image encryption hardware accelerator based on our FCNT architecture achieves the fastest processing speed, requiring only 0.505 ms to encrypt a single 256 × 256 grayscale image, with a throughput of 1038 Mbps.
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基于快速余弦数变换的图像加密/解密加速器
余弦数变换(CNT)及其快速余弦数变换(FCNT)由于其模块化算法提高了计算精度,在图像加密中得到了广泛的应用。然而,现有的FCNT硬件架构存在计算周期长、资源消耗高的问题,难以满足快速图像加密的需求。本文提出了一种采用流水线和时分复用方法的无乘法器(MM)八点FCNT硬件架构。在此基础上,实现了一个图像加密硬件加速器。实验结果表明,与现有方法相比,所提出的FCNT架构的计算延迟降低了18.2%,lut使用率降低了18.5%,FFs使用率降低了21.7%。此外,与目前最先进的技术相比,基于FCNT架构的图像加密硬件加速器实现了最快的处理速度,加密单个256 × 256灰度图像仅需0.505 ms,吞吐量为1038 Mbps。
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来源期刊
Integration-The Vlsi Journal
Integration-The Vlsi Journal 工程技术-工程:电子与电气
CiteScore
3.80
自引率
5.30%
发文量
107
审稿时长
6 months
期刊介绍: Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.
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