Zhiqiang Xu, Zhenmin Li, Feng Han, Xiaolei Wang, Gaoming Du
{"title":"Image encryption/decryption accelerator based on Fast Cosine Number Transform","authors":"Zhiqiang Xu, Zhenmin Li, Feng Han, Xiaolei Wang, Gaoming Du","doi":"10.1016/j.vlsi.2025.102416","DOIUrl":null,"url":null,"abstract":"<div><div>The Cosine Number Transform (CNT) and its Fast Cosine Number Transform (FCNT) are widely used in image encryption due to their modular arithmetic, which enhances computational accuracy. However, existing hardware architectures for FCNT suffer from long computation cycles and high resource consumption, making it challenging to meet the demands for fast image encryption. This paper proposes an eight-point FCNT hardware architecture with multiplier-less multiplication (MM), employing pipeline and time-division multiplexing methods. Based on this architecture, an image encryption hardware accelerator was implemented. Experimental results show that compared to existing methods, the proposed FCNT architecture reduces computational delay by 18.2%and decreases LUTs usage by 18.5% and FFs usage by 21.7%. Furthermore, compared to the current state-of-the-art, the image encryption hardware accelerator based on our FCNT architecture achieves the fastest processing speed, requiring only 0.505 ms to encrypt a single 256 × 256 grayscale image, with a throughput of 1038 Mbps.</div></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":"103 ","pages":"Article 102416"},"PeriodicalIF":2.5000,"publicationDate":"2025-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926025000732","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
The Cosine Number Transform (CNT) and its Fast Cosine Number Transform (FCNT) are widely used in image encryption due to their modular arithmetic, which enhances computational accuracy. However, existing hardware architectures for FCNT suffer from long computation cycles and high resource consumption, making it challenging to meet the demands for fast image encryption. This paper proposes an eight-point FCNT hardware architecture with multiplier-less multiplication (MM), employing pipeline and time-division multiplexing methods. Based on this architecture, an image encryption hardware accelerator was implemented. Experimental results show that compared to existing methods, the proposed FCNT architecture reduces computational delay by 18.2%and decreases LUTs usage by 18.5% and FFs usage by 21.7%. Furthermore, compared to the current state-of-the-art, the image encryption hardware accelerator based on our FCNT architecture achieves the fastest processing speed, requiring only 0.505 ms to encrypt a single 256 × 256 grayscale image, with a throughput of 1038 Mbps.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.