Analysis of Power Consumption and Propagation Delay in Voltage Level Shifters

Abstract

The analysis of the operation of nonlinear circuits, such as voltage level shifters and latched comparators, and therefore the prediction of their propagation delay and power consumption, is challenging. This is because the operating points of the employed nonlinear devices are time-varying. Hence, in this letter, a new approach which uses the trajectory of the operating points of the employed devices is proposed to analyze nonlinear circuits. The proposed method is used to provide a comprehensive study about the operation of the cross-coupled voltage level shifters. The proposed analysis not only formulates the existing contention between the pull-up and pull-down devices but also presents closed-form formulas for the delay as well as the power consumption. Measurement results of a prototype implemented in a standard 0.18- $\mu $ m CMOS technology verify the effectiveness of the proposed method.