Design and Optimization of Dual Material Gate Junctionless FinFET Using Dimensional Effect, Gate Oxide and Workfunction Engineering at 7 nm Technology Node

Abstract

In this paper, we designed and analyzed the performance of Dual Material Gate Junctionless FinFET(DMG JLFinFET) using gate engineering with high-k dielectrics for nanoscale applications. Here first we optimized the doping and later optimized the work function. Thereafter by using these optimized values we carried our work for other simulations. Various high-k materials are used as gate oxide. We found that by replacing gate oxide with high-k materials the device performance is improved in terms of I_on/I_off, SS, and DIBL. The fine tuning of gate workfunction reduces short channel effects (SCEs). In Fin width (F_W) variation, single gate oxide HfO₂ has 61.29 mV/dec and 16.03 mV/V, dual gate-oxide Si₃N₄ + HfO₂ has 61.22 mV/dec and 18.49 mV/V as SS and DIBL, respectively. In Fin height (F_H) variation single gate oxide HfO₂ has 63.04 mV/V and 27.11 mV/V, dual gate oxide Si₃N₄ + HfO₂ has 62.57 mV/V and 26.05 mV/V as SS and DIBL, respectively. I_on/I_off is improved to 0.78 × 10⁷ using HfO₂ and 1.25 × 10⁷ using Si₃N₄ + HfO₂ as gate oxides. The ratio of I_on/I_off with F_H and F_W variation provide evidence that the DMG JLFinFET is best competent for low power nanoscale applications. 3-D simulations are done using Cogenda genius Visual TCAD.