Influence of copper pillar bump structure on flip chip packaging during reflow soldering: a numerical approach

IF 0.7 4区 工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC Microelectronics International Pub Date : 2021-09-23 DOI:10.1108/mi-05-2021-0044
M. Ishak, M. Aziz, F. Ismail, M. Z. Abdullah
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引用次数: 1

Abstract

Purpose The purpose of this paper is to present the experimental and simulation studies on the influence of copper pillar bump structure on flip chip packaging during reflow soldering. Design/methodology/approach In this work, solidification/melting modelling and volume of fluid modelling were used. Reflow soldering process of Cu pillar type FC was modelled using computational fluid dynamic software (FLUENT). The experimental results have been validated with the simulation results to prove the accuracy of the numerical method. Findings The findings of this study reveal that solder volume is the most important element influencing reflow soldering. The solder cap volume reduces as the Cu pillar bump diameter lowers, making the reflow process more difficult to establish a good solder union, as less solder is allowed to flow. Last but not least, the solder cap height for the reflow process must be optimized to enable proper solder joint formation. Practical implications This study provides a basis and insights into the impact of copper pillar bump structure on flip chip packaging during reflow soldering that will be advancing the future design of 3D stack package. This study also provides a superior visualization and knowledge of the melting and solidification phenomenon during the reflow soldering process. Originality/value The computational fluid dynamics analysis of copper pillar bump structure on flip chip packaging during reflow soldering is scant. To the authors’ best knowledge, no research has been concentrated on copper pillar bump size configurations in a thorough manner. Without the in-depth study, copper pillar bump size might have the impact of copper pillar bump structure on flip chip packaging during reflow soldering. Five design of parameter of flip chip IC package model was proposed for the investigation of copper pillar bump structure on flip chip packaging during reflow soldering.
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回流焊过程中铜柱凹凸结构对倒装芯片封装的影响:数值方法
目的对回流焊过程中铜柱凹凸结构对倒装封装的影响进行了实验和仿真研究。设计/方法/方法在这项工作中,使用了凝固/熔化建模和流体体积建模。利用计算流体动力学软件FLUENT对铜柱型FC的回流焊过程进行了建模。实验结果与仿真结果进行了验证,验证了数值方法的准确性。研究结果表明,焊料体积是影响回流焊效果的最重要因素。随着铜柱凸点直径的减小,焊帽体积减小,使得回流过程更难建立良好的焊料结合,因为允许流动的焊料减少。最后但并非最不重要的是,回流工艺的焊帽高度必须优化,以使适当的焊点形成。实际意义本研究为研究回流焊过程中铜柱凹凸结构对倒装封装的影响提供了基础和见解,将推动未来3D堆叠封装的设计。本研究还提供了回流焊过程中熔化和凝固现象的可视化和知识。对倒装芯片封装中回流焊过程中铜柱凸点结构的计算流体动力学分析还很缺乏。据作者所知,目前还没有对铜柱凹凸尺寸配置进行深入的研究。如果没有深入的研究,回流焊过程中铜柱凸点的尺寸可能会对倒装芯片封装产生影响。提出了倒装IC封装模型参数的五种设计方法,以研究倒装封装回流焊过程中铜柱凹凸结构的影响。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
Microelectronics International
Microelectronics International 工程技术-材料科学:综合
CiteScore
1.90
自引率
9.10%
发文量
28
审稿时长
>12 weeks
期刊介绍: Microelectronics International provides an authoritative, international and independent forum for the critical evaluation and dissemination of research and development, applications, processes and current practices relating to advanced packaging, micro-circuit engineering, interconnection, semiconductor technology and systems engineering. It represents a current, comprehensive and practical information tool. The Editor, Dr John Atkinson, welcomes contributions to the journal including technical papers, research papers, case studies and review papers for publication. Please view the Author Guidelines for further details. Microelectronics International comprises a multi-disciplinary study of the key technologies and related issues associated with the design, manufacture, assembly and various applications of miniaturized electronic devices and advanced packages. Among the broad range of topics covered are: • Advanced packaging • Ceramics • Chip attachment • Chip on board (COB) • Chip scale packaging • Flexible substrates • MEMS • Micro-circuit technology • Microelectronic materials • Multichip modules (MCMs) • Organic/polymer electronics • Printed electronics • Semiconductor technology • Solid state sensors • Thermal management • Thick/thin film technology • Wafer scale processing.
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