Design and Analysis of a Resistive Sensor Interface With Phase Noise-Energy-Resolution Scalability for a Time-Based Resistance-to-Digital Converter

IF 1.9 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Frontiers in electronics Pub Date : 2022-04-25 DOI:10.3389/felec.2022.792326
Dong-Hyun Seo, Baibhab Chatterjee, S. Scott, D. Valentino, D. Peroulis, Shreyas Sen
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引用次数: 2

Abstract

This article presents the design and analysis of a resistive sensor interface with three different designs of phase noise-energy-resolution scalability in time-based resistance-to-digital converters (RDCs), including test chip implementations and measurements, targeted toward either minimizing the energy/conversion step or maximizing bit-resolution. The implemented RDCs consist of a three-stage differential ring oscillator, which is current starved using the resistive sensor, a differential-to-single-ended amplifier, and digital modules and serial interface. The first RDC design (baseline) included the basic structure of time-based RDC and targeted low-energy/conversion step. The second RDC design (goal: higher-resolution) aimed to improve the rms jitter/phase noise of the oscillator with help of speed-up latches, to achieve high bit-resolution as compared to the first RDC design. The third RDC design (goal: process portability) reduced the power consumption by scaling the technology with the improved phase-noise design, achieving 1-bit better resolution as that of the second RDC design. Using time-based implementation, the RDCs exhibit energy-resolution scalability and consume a measured power of 861 nW with 18-bit resolution in design 1 in TSMC 0.35 μm technology (with 10 ms read-time, with one readout every second). Measurements of designs 2 and 3 demonstrate power consumption of 19.2 μW with 20-bit resolution using TSMC 0.35μm and 17.6 μW with 20-bit resolution using TSMC 0.18μm, respectively (both with 10 ms read-time, repeated every second). With 30 ms read-time, design 3 achieves 21-bit resolution, which is the highest resolution reported for a time-based ADC. The 0.35-μm time-based RDC is the lowest-power time-based ADC reported, while the 0.18-μm time-based RDC with speed-up latch offers the highest resolution. The active chip-area for all three designs is less than 1.1 mm2.
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基于时间的电阻-数字转换器中具有相位噪声-能量分辨率可扩展性的电阻传感器接口的设计与分析
本文介绍了基于时间的电阻-数字转换器(rdc)中具有三种不同相位噪声-能量分辨率可扩展性设计的电阻传感器接口的设计和分析,包括测试芯片的实现和测量,目标是最小化能量/转换步骤或最大化位分辨率。实现的rdc包括一个三级差分环振荡器,该振荡器使用电阻传感器进行电流饥渴,一个差分到单端放大器,以及数字模块和串行接口。第一个RDC设计(基线)包括基于时间的RDC的基本结构和目标低能量/转换步骤。第二个RDC设计(目标:更高的分辨率)旨在通过加速锁存器改善振荡器的有效值抖动/相位噪声,以实现与第一个RDC设计相比的高比特分辨率。第三种RDC设计(目标:过程可移植性)通过改进的相位噪声设计扩展技术,降低了功耗,实现了比第二种RDC设计高1位的分辨率。采用基于时间的实现,rdc具有能量分辨率可扩展性,并且在设计1中采用台积电0.35 μm技术(读取时间为10 ms,每秒读取一次)的18位分辨率下消耗861 nW的测量功率。设计2和设计3的功耗分别为19.2 μW(20位分辨率,采用TSMC 0.35μm)和17.6 μW(20位分辨率,采用TSMC 0.18μm)(读取时间均为10 ms,每秒重复)。通过30ms的读取时间,设计3实现了21位分辨率,这是基于时间的ADC的最高分辨率。基于0.35 μm时间的RDC是目前所报道的功耗最低的基于时间的ADC,而带有加速锁存器的基于0.18 μm时间的RDC提供了最高的分辨率。三种设计的有效芯片面积均小于1.1 mm2。
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