Single event upset reinforcement technology of DICE flip-flop based on layout design

Abstract

D flip-flop is the basis of timing logic circuit, and SEMU phenomenon tends to be serious with the integrated circuit process size shrinking to nanometer scale. The anti-SEU ability based on DICE structure for D flip-flop cannot meet the requirements of aerospace engineering. Based on the SEU reinforcement technology of D flip-flop under nano-technology and the SEU mechanism of DICE structure, a layout-level anti-SEU flip-flop design method based on DICE circuit structure is proposed considering the circuit performance, area, power consumption and other resource costs. And then a D flip-flop with SEU resistance is designed by commercial 65 nm process, and the designed flip-flop area is 1.8 times that of commercial structure flip-flop. The function and and radiation simulation results indicate that the establishment time and transmission delay of the flip-flop are equivalent to those of the commercial one, and no SEU occurs under the Ge ion bombardment with the LET threshold of approximately 37 MeV·cm2/mg. The performance of the flip-flop circuit and the ability to resist single particle soft error are excellent. In the anti-radiation ASIC design, the area, wiring resources and timing overhead caused by the reinforcement of the D flip-flop circuit are greatly saved.