Low Power High Performance 8bit Vedic Multiplier Using 16nm

Abstract

In this paper, an 8-bit Vedic multiplier is designed. The performance of the system basically works better if the performance of the multiplier is good. In today's digital time, Multiplier is one which consumes power at the same time speed of multiplier is playing very important aspects in this. Multiplier Optimization for power and delay both will play an important role. Adders such as Ripple carry adder and carry look-ahead adder and carry skip adder are also having a role in the selection of adder units in the multiplier. Here all the three adders are designed using transmission gates and compared using CMOS.