Implementation of High-Speed Serial I/O using Xilinx Tools in FPGA

Abstract

The I/O (Input Output) module conveys the information between I/O device and processor. I/O devices are majorly of two types: Parallel I/O and Serial I/O. Parallel I/O performs multiple I/O operations simultaneously. Due to this speed and higher bandwidths are achieved, but the usage of parallel I/O devices is decreasing as time progresses because it involves complex design due to the usage of multiple wires for the transmission hence only limited to usage in shorter distances. It also uses a greater number of pins compared to serial I/O for the same number of data bits which makes its usage problematic in higher level devices. Serial I/O transmits individual data bits sequentially. It uses lesser number of lines for data transmission thereby reducing the design complexity. Since, the data transmission is sequential the signal delay increases. Thus, this project aims to develop a protocol which achieves High Speed Serial I/O which helps to increase the data rate from Mbps to Gbps, decrease the design complexity, to design hardware using fewer number of pins on PCB and reduce signal delay to maximum extent possible