Magnitude Comparison and Sign Detection based on the 4-Moduli Set {2n+1, 2n−1, 2n+3, 2n−3}

Mohsen Mojahed, Amir Sabbagh Molahossein, Azadeh Alsadat Emrani Zarandi
{"title":"Magnitude Comparison and Sign Detection based on the 4-Moduli Set {2n+1, 2n−1, 2n+3, 2n−3}","authors":"Mohsen Mojahed, Amir Sabbagh Molahossein, Azadeh Alsadat Emrani Zarandi","doi":"10.52547/mjee.15.3.93","DOIUrl":null,"url":null,"abstract":": The 4-moduli set residue number system (RNS), {2 𝑛 + 3,2 𝑛 − 3,2 𝑛 + 1, 2 𝑛 − 1} , with a wide dynamic range, has recently been proposed as a balanced 4-moduli set for utilizing the cases that demand fast calculations such as deep learning and implementation of asymmetric cryptographic algorithms. Up to now, only an unsigned reverse converter has been designed for this moduli set. Thus, there is a need for two separate units, a sign detection circuit, and a comparator to use this set in cases requiring sign and comparison. Nevertheless, the existence of these components demands high hardware that makes the implementation of the RNS impractical. Therefore, this paper presents the design of a sign detection circuit and a signed reverse converter that can overcome this problem by reusing the hardware. To achieve an integrated hardware design, first, we optimized the previous unsigned reverse converter for this 4-moduli set and next, we derived an approach from the structure of the reverse convertor for detecting signs and recognizing comparators. Finally, using the sign signals extracted from the reverse converter, we change reverse convertor into a unit that perform sign detection and comparison. The simulation has been conducted using ISE Design Suite 14.7 tool and the Spartan6 family technology. Empirical results show that, the proposed multifunctional unit has an approximately identical performance with respect to delay and area compared to the previous reverse converter. Besides, the proposed signed reverse converter relies on a 46% and 28% reduction in area and delay compared to the previous unsigned reverse converter which uses a comparator and also a multiplexer to detect a sign in the output.","PeriodicalId":37804,"journal":{"name":"Majlesi Journal of Electrical Engineering","volume":" ","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Majlesi Journal of Electrical Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.52547/mjee.15.3.93","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"Engineering","Score":null,"Total":0}
引用次数: 0

Abstract

: The 4-moduli set residue number system (RNS), {2 𝑛 + 3,2 𝑛 − 3,2 𝑛 + 1, 2 𝑛 − 1} , with a wide dynamic range, has recently been proposed as a balanced 4-moduli set for utilizing the cases that demand fast calculations such as deep learning and implementation of asymmetric cryptographic algorithms. Up to now, only an unsigned reverse converter has been designed for this moduli set. Thus, there is a need for two separate units, a sign detection circuit, and a comparator to use this set in cases requiring sign and comparison. Nevertheless, the existence of these components demands high hardware that makes the implementation of the RNS impractical. Therefore, this paper presents the design of a sign detection circuit and a signed reverse converter that can overcome this problem by reusing the hardware. To achieve an integrated hardware design, first, we optimized the previous unsigned reverse converter for this 4-moduli set and next, we derived an approach from the structure of the reverse convertor for detecting signs and recognizing comparators. Finally, using the sign signals extracted from the reverse converter, we change reverse convertor into a unit that perform sign detection and comparison. The simulation has been conducted using ISE Design Suite 14.7 tool and the Spartan6 family technology. Empirical results show that, the proposed multifunctional unit has an approximately identical performance with respect to delay and area compared to the previous reverse converter. Besides, the proposed signed reverse converter relies on a 46% and 28% reduction in area and delay compared to the previous unsigned reverse converter which uses a comparator and also a multiplexer to detect a sign in the output.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
基于4模集{2n+1,2n-1,2n+3,2n-3}的幅值比较和符号检测
4模集剩数系统(RNS){2𝑛+ 3,2𝑛−3,2𝑛+ 1,2𝑛−1},具有广泛的动态范围,最近被提出作为一个平衡的4模集,用于利用需要快速计算的情况,如深度学习和非对称密码算法的实现。到目前为止,针对这个模集只设计了一个无符号反向转换器。因此,需要两个独立的单元,一个符号检测电路和一个比较器,以便在需要符号和比较的情况下使用该集合。然而,这些组件的存在对硬件的要求很高,这使得RNS的实现不切实际。因此,本文设计了一种符号检测电路和一种符号反向转换器,通过硬件的复用来克服这一问题。为了实现集成硬件设计,首先,我们针对这个4模集优化了之前的无符号反向转换器,然后,我们从反向转换器的结构中推导出一种检测符号和识别比较器的方法。最后,利用从反向变换器中提取的符号信号,将反向变换器改造成一个进行符号检测和比较的单元。仿真使用ISE Design Suite 14.7工具和Spartan6系列技术进行。实验结果表明,与之前的反向变换器相比,所提出的多功能单元在延迟和面积方面具有大致相同的性能。此外,与之前使用比较器和多路复用器检测输出中的符号的无符号反向转换器相比,所提出的有符号反向转换器依赖于46%和28%的面积和延迟减少。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
Majlesi Journal of Electrical Engineering
Majlesi Journal of Electrical Engineering Engineering-Electrical and Electronic Engineering
CiteScore
1.20
自引率
0.00%
发文量
9
期刊介绍: The scope of Majlesi Journal of Electrcial Engineering (MJEE) is ranging from mathematical foundation to practical engineering design in all areas of electrical engineering. The editorial board is international and original unpublished papers are welcome from throughout the world. The journal is devoted primarily to research papers, but very high quality survey and tutorial papers are also published. There is no publication charge for the authors.
期刊最新文献
Three's a crowd? Examining evolving public transit crowding standards amidst the COVID-19 pandemic. Circuit Models to Study the Radiated and Conducted Susceptibilities of Multiconductor Shielded Cables Connected to Non-linear Load A CMOS Low-Power Noise Shaping-Enhanced SMASH ΣΔ Modulator A Novel High Voltage Gain Buck-Boost Converter with Dual Mode Boost A New Low Power, Area Efficient 4-bit Carry Look Ahead Adder in CNFET Technology
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1