{"title":"OTA Based Mem-capacitor Validation and Implementation Using Commercially Available IC","authors":"Chandra Shankar, Anuj Nagar, Ashutosh Singh, Ankleshwar Kumar","doi":"10.24425/ijet.2023.146511","DOIUrl":null,"url":null,"abstract":"— This paper discusses a mem-capacitor circuit which is based on two MO-OTA along with a multiplier and 4 passive elements. This circuit is a charge-controlled memcapacitor emulator which is independent of any memristor also it consists the feature of electronic tunability. Additionally, this circuit is simpler and uses less hardware because it lacks a mutator and uses fewer active-passive components. The circuit behaviour is justified through various simulations in cadence Orcad tool with 180nm CMOS TSMC parameters. Additionally, conclusions from simulations and theory are validated experimentally through commercially available IC.","PeriodicalId":13922,"journal":{"name":"International Journal of Electronics and Telecommunications","volume":" ","pages":""},"PeriodicalIF":0.5000,"publicationDate":"2023-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Electronics and Telecommunications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.24425/ijet.2023.146511","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"TELECOMMUNICATIONS","Score":null,"Total":0}
引用次数: 0
Abstract
— This paper discusses a mem-capacitor circuit which is based on two MO-OTA along with a multiplier and 4 passive elements. This circuit is a charge-controlled memcapacitor emulator which is independent of any memristor also it consists the feature of electronic tunability. Additionally, this circuit is simpler and uses less hardware because it lacks a mutator and uses fewer active-passive components. The circuit behaviour is justified through various simulations in cadence Orcad tool with 180nm CMOS TSMC parameters. Additionally, conclusions from simulations and theory are validated experimentally through commercially available IC.