Review of Simulation Methods for Design of Spin Logic

Abstract

While the scaling of CMOS electronics continues and reaches the sub-10 nanometer range, active research is being conducted on logic devices beyond CMOS to find a path to a more energy efficient integrated circuit platform for computing. Among them, a prominent option is spintronic devices, remarkable for their non-volatility and low switching energy. Simulation is the key part of this research due to spintronics’ reliance on novel materials, device structures, and circuit architecture. We review recent publications which often traverse these hierarchical levels of the computing stack. Prevalent methods, comparison with experiments, use in proposing new logic concepts are surveyed.