Pub Date : 2023-12-01DOI: 10.1109/mnano.2023.3316876
M. B. Lodi, R. Sliz, Kremena Makasheva
{"title":"The MENED Program at Nanotechnology Council [Column]","authors":"M. B. Lodi, R. Sliz, Kremena Makasheva","doi":"10.1109/mnano.2023.3316876","DOIUrl":"https://doi.org/10.1109/mnano.2023.3316876","url":null,"abstract":"","PeriodicalId":44724,"journal":{"name":"IEEE Nanotechnology Magazine","volume":"120 50","pages":""},"PeriodicalIF":1.6,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138608935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-01DOI: 10.1109/MNANO.2023.3297105
S. Ki, Mingze Chen, Xiaogan Liang
Short-term plasticity (STP) and long-term potentiation (LTP) properties of neural synapses are crucial for developing complex neuromorphic systems and functions. In this work, we fabricated two-terminal memristors with multi-layer MoS2 channels and investigated pulse-programmed short-term and long-term synaptic responses. This work indicates that MoS2 memristors exhibit different magnitudes of STP and LTP effects under different pulse programming settings. Specifically, we utilized the paired-pulse facilitation (PPF) function for fitting experimentally measured relaxation curves of MoS2 memristors to quantitatively evaluate the relative dominance of STP and LTP effects. Such analytic results show that the absolute magnitudes of both STP and LTP effects in a memristor increase with increasing pulse frequency, pulse voltage (or amplitude), pulse duty cycle, and a total number of applied pulses, whereas the relative dominance levels of these two effects are typically not in a simple monotonous relationship with these pulse parameters. This indicates that the programming pulse parameters profoundly affect pulse-field-mediated charge trapping and S-vacancy migration processes which are responsible for the observed STP and LTP effects, respectively. This work provides a useful guideline for activating STP and LTP effects in emerging memristive devices based on 2D layered semiconductors, which could be deployed for making synaptic nodes in hardware-based artificial neural networks or neuromorphic sensory devices capable of sensing spatiotemporal events.
{"title":"Pulse-Programmed Short-Term Plasticity and Long-Term Potentiation of MoS2 Memristive Devices","authors":"S. Ki, Mingze Chen, Xiaogan Liang","doi":"10.1109/MNANO.2023.3297105","DOIUrl":"https://doi.org/10.1109/MNANO.2023.3297105","url":null,"abstract":"Short-term plasticity (STP) and long-term potentiation (LTP) properties of neural synapses are crucial for developing complex neuromorphic systems and functions. In this work, we fabricated two-terminal memristors with multi-layer MoS2 channels and investigated pulse-programmed short-term and long-term synaptic responses. This work indicates that MoS2 memristors exhibit different magnitudes of STP and LTP effects under different pulse programming settings. Specifically, we utilized the paired-pulse facilitation (PPF) function for fitting experimentally measured relaxation curves of MoS2 memristors to quantitatively evaluate the relative dominance of STP and LTP effects. Such analytic results show that the absolute magnitudes of both STP and LTP effects in a memristor increase with increasing pulse frequency, pulse voltage (or amplitude), pulse duty cycle, and a total number of applied pulses, whereas the relative dominance levels of these two effects are typically not in a simple monotonous relationship with these pulse parameters. This indicates that the programming pulse parameters profoundly affect pulse-field-mediated charge trapping and S-vacancy migration processes which are responsible for the observed STP and LTP effects, respectively. This work provides a useful guideline for activating STP and LTP effects in emerging memristive devices based on 2D layered semiconductors, which could be deployed for making synaptic nodes in hardware-based artificial neural networks or neuromorphic sensory devices capable of sensing spatiotemporal events.","PeriodicalId":44724,"journal":{"name":"IEEE Nanotechnology Magazine","volume":"17 1","pages":"24-29"},"PeriodicalIF":1.6,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46593182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-01DOI: 10.1109/MNANO.2023.3297106
Y. Huang, Vignesh Ravichandran, Wuyu Zhao, Q. Xia
Computing hardware is one of the crucial drivers of artificial intelligence (AI) that impacts our daily lives. However, despite the significant improvements made in recent decades, the energy consumption of computing hardware that powers AI, especially deep neural networks, remains considerably higher than that of human brains. Hardware innovations based on emerging nanodevices like memristors offer potential solutions to energy-efficient computing systems. This review discusses the challenges associated with developing energy-efficient computing hardware based on memristive nanodevices and summarizes recent progress in memristive devices, crossbar arrays, systems, and algorithms, aiming at addressing these issues from a bottom-up approach. Potential research directions are proposed to further improve future computing hardware's energy efficiency.
{"title":"Towards Energy-Efficient Computing Hardware Based on Memristive Nanodevices","authors":"Y. Huang, Vignesh Ravichandran, Wuyu Zhao, Q. Xia","doi":"10.1109/MNANO.2023.3297106","DOIUrl":"https://doi.org/10.1109/MNANO.2023.3297106","url":null,"abstract":"Computing hardware is one of the crucial drivers of artificial intelligence (AI) that impacts our daily lives. However, despite the significant improvements made in recent decades, the energy consumption of computing hardware that powers AI, especially deep neural networks, remains considerably higher than that of human brains. Hardware innovations based on emerging nanodevices like memristors offer potential solutions to energy-efficient computing systems. This review discusses the challenges associated with developing energy-efficient computing hardware based on memristive nanodevices and summarizes recent progress in memristive devices, crossbar arrays, systems, and algorithms, aiming at addressing these issues from a bottom-up approach. Potential research directions are proposed to further improve future computing hardware's energy efficiency.","PeriodicalId":44724,"journal":{"name":"IEEE Nanotechnology Magazine","volume":"17 1","pages":"30-38"},"PeriodicalIF":1.6,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43997568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-01DOI: 10.1109/mnano.2023.3297118
Guilherme Migliato Marega, Zhenyu Wang, Yanfei Zhao, Hyun Goo Ji, Asmund Ottesen, Mukesh Tripathi, Aleksandra Radenovic, Andras Kis
Memory devices have returned to the spotlight due to increasing interest in using in-memory computing architectures to make data-driven algorithms more energy-efficient. One of the main advantages of this architecture is the efficient performance of vector-matrix multiplications while avoiding the “von Neumann bottleneck.” Despite these promises, no single material platform meets all the requirements for the fabrication of this new processor technology. Recently, flash memories based on monolayer MoS2 have been shown to achieve ultra-fast operation, overcoming one of the main drawbacks of this memory type. Together with its other characteristics, this makes them a promising candidate for the base elements of this technology. However, the question remains of how to achieve large-area ultra-fast operation of MoS2 monolayer flash memories. In this work, we will compare large-area flash memories based on MoS2 used in past realizations of in-memory systems and analyze the improvements needed to achieve ultra-fast performance for in-memory applications.
{"title":"How to Achieve Large-Area Ultra-Fast Operation of MoS<sub>2</sub> Monolayer Flash Memories?","authors":"Guilherme Migliato Marega, Zhenyu Wang, Yanfei Zhao, Hyun Goo Ji, Asmund Ottesen, Mukesh Tripathi, Aleksandra Radenovic, Andras Kis","doi":"10.1109/mnano.2023.3297118","DOIUrl":"https://doi.org/10.1109/mnano.2023.3297118","url":null,"abstract":"Memory devices have returned to the spotlight due to increasing interest in using in-memory computing architectures to make data-driven algorithms more energy-efficient. One of the main advantages of this architecture is the efficient performance of vector-matrix multiplications while avoiding the “von Neumann bottleneck.” Despite these promises, no single material platform meets all the requirements for the fabrication of this new processor technology. Recently, flash memories based on monolayer MoS2 have been shown to achieve ultra-fast operation, overcoming one of the main drawbacks of this memory type. Together with its other characteristics, this makes them a promising candidate for the base elements of this technology. However, the question remains of how to achieve large-area ultra-fast operation of MoS2 monolayer flash memories. In this work, we will compare large-area flash memories based on MoS2 used in past realizations of in-memory systems and analyze the improvements needed to achieve ultra-fast performance for in-memory applications.","PeriodicalId":44724,"journal":{"name":"IEEE Nanotechnology Magazine","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135324013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-01DOI: 10.1109/mnano.2023.3300069
Bing Sheu, Shao-Ku Kao
This Special Issue includes five outstanding papers. The first three papers are contributed by 2023 IEEE Fellows who were elected via the Nanotechnology Council. The IEEE Fellow citation for Prof. Xiaoning Jiang is “for contributions to ultrasound transducers for advanced sensing, imaging, and therapy.” The IEEE Fellow citation for Prof. Qiangfei Xia is “for contributions to resistive memory arrays and devices for in memory computing.” The IEEE Fellow citation for Prof. Andras Kis is “for contributions to the development of 2D materials and electronic devices.”
{"title":"The Editors’ Desk [The Editors' Desk]","authors":"Bing Sheu, Shao-Ku Kao","doi":"10.1109/mnano.2023.3300069","DOIUrl":"https://doi.org/10.1109/mnano.2023.3300069","url":null,"abstract":"This Special Issue includes five outstanding papers. The first three papers are contributed by 2023 IEEE Fellows who were elected via the Nanotechnology Council. The IEEE Fellow citation for Prof. Xiaoning Jiang is “for contributions to ultrasound transducers for advanced sensing, imaging, and therapy.” The IEEE Fellow citation for Prof. Qiangfei Xia is “for contributions to resistive memory arrays and devices for in memory computing.” The IEEE Fellow citation for Prof. Andras Kis is “for contributions to the development of 2D materials and electronic devices.”","PeriodicalId":44724,"journal":{"name":"IEEE Nanotechnology Magazine","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135452012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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