Phone-nomenon 2.0: A compact thermal model for smartphones

IF 1.1 4区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IET Computers and Digital Techniques Pub Date : 2023-01-08 DOI:10.1049/cdt2.12052
Yu-Min Lee, Hong-Wen Chiou, Shinyu Shiau, Chi-Wen Pan, Shih-Hung Ting
{"title":"Phone-nomenon 2.0: A compact thermal model for smartphones","authors":"Yu-Min Lee,&nbsp;Hong-Wen Chiou,&nbsp;Shinyu Shiau,&nbsp;Chi-Wen Pan,&nbsp;Shih-Hung Ting","doi":"10.1049/cdt2.12052","DOIUrl":null,"url":null,"abstract":"<p>This paper presents a compact thermal model for smartphones, Phone-nomenon 2.0, to predict the thermal behavior of smartphones. In the beginning, non-linearities of internal and external heat transfer mechanisms of smartphones and a compact thermal model for these non-linearities have been studied and proposed. Then, an iterative simulation procedure to handle these non-linearities was developed, and the basic simulation framework which is one option in Phone-nomenon 2.0 was established and we call it Phone-nomenon.Iter. Finally, the linearisation approach was applied, and model order reduction techniques to enhance and speed up the basic framework were employed, and these two options Phone-nomenon.Lin and Phone-nomenon.LinMOR were named. Compared with a commercial tool, ANSYS Icepak, Phone-nomenon.Iter can achieve two orders of magnitude speedup with the maximum error being less than 1.90% for steady-state simulations and three orders of magnitude speedup with the temperature difference being less than 0.65°C for transient simulations. In addition, the speedup of Phone-nomenon.Lin over Phone-nomenon.Iter can be at least 4.22× and 3.26× for steady-state and transient simulations, respectively. Moreover, the speedup of Phone-nomenon.LinMOR over Phone-nomenon.Lin is at least 2.57×.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"17 2","pages":"43-59"},"PeriodicalIF":1.1000,"publicationDate":"2023-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12052","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IET Computers and Digital Techniques","FirstCategoryId":"94","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1049/cdt2.12052","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

Abstract

This paper presents a compact thermal model for smartphones, Phone-nomenon 2.0, to predict the thermal behavior of smartphones. In the beginning, non-linearities of internal and external heat transfer mechanisms of smartphones and a compact thermal model for these non-linearities have been studied and proposed. Then, an iterative simulation procedure to handle these non-linearities was developed, and the basic simulation framework which is one option in Phone-nomenon 2.0 was established and we call it Phone-nomenon.Iter. Finally, the linearisation approach was applied, and model order reduction techniques to enhance and speed up the basic framework were employed, and these two options Phone-nomenon.Lin and Phone-nomenon.LinMOR were named. Compared with a commercial tool, ANSYS Icepak, Phone-nomenon.Iter can achieve two orders of magnitude speedup with the maximum error being less than 1.90% for steady-state simulations and three orders of magnitude speedup with the temperature difference being less than 0.65°C for transient simulations. In addition, the speedup of Phone-nomenon.Lin over Phone-nomenon.Iter can be at least 4.22× and 3.26× for steady-state and transient simulations, respectively. Moreover, the speedup of Phone-nomenon.LinMOR over Phone-nomenon.Lin is at least 2.57×.

Abstract Image

查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
手机nomenon 2.0:一款适用于智能手机的紧凑型散热机型
本文提出了一个紧凑的智能手机热模型,Phone nomenon 2.0,用于预测智能手机的热行为。首先,研究并提出了智能手机内部和外部传热机制的非线性,以及这些非线性的紧凑热模型。然后,开发了一个处理这些非线性的迭代仿真程序,并建立了Phone nomenon 2.0中的一个基本仿真框架,我们称之为Phone-nomenon.it。最后,应用了线性化方法,并采用了模型降阶技术来增强和加速基本框架,并将这两个选项命名为Phone-nomnon.Lin和Phone-nomNon.LinMOR。与商业工具ANSYS Icepak相比,Phone-nomnon.Iter可以实现两个数量级的加速,稳态模拟的最大误差小于1.90%,瞬态模拟的加速可以实现三个数量级,温差小于0.65°C。此外,对于稳态和瞬态模拟,Phone-nomnon.Lin比Phone-nomNon.Iter的加速率分别至少为4.22倍和3.26倍。此外,Phone-nomenon.LinMOR比Phone-nomnon.Lin的加速率至少为2.57×。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
IET Computers and Digital Techniques
IET Computers and Digital Techniques 工程技术-计算机:理论方法
CiteScore
3.50
自引率
0.00%
发文量
12
审稿时长
>12 weeks
期刊介绍: IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.
期刊最新文献
E-Commerce Logistics Software Package Tracking and Route Planning and Optimization System of Embedded Technology Based on the Intelligent Era A Configurable Accelerator for CNN-Based Remote Sensing Object Detection on FPGAs A FPGA Accelerator of Distributed A3C Algorithm with Optimal Resource Deployment An Efficient RTL Design for a Wearable Brain–Computer Interface Adaptive Shrink and Shard Architecture Design for Blockchain Storage Efficiency
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1