Design of fully differential fast SCL Schmitt-trigger delay element with tunable delay and hysteresis in design and run-time

Abstract

Tuning the delay of the circuit during the circuit performance can give a chance to a circuit to reduce Process, Voltage and Temperature (PVT) effects on delay and frequency by resetting its delay in feedback. This paper presented a full differential Schmitt-trigger (ST) with tunable delay and hysteresis. The delay-hysteresis setting is done in the design phase by tuning the biasing current, sizing, bias voltage and also during the execute phase (run time) by a digital bit and restructuring the circuit and delay route. The presented ST can have high and low delays with different frequencies using a digital bit in the circuit. This can help the band selection for multi-band applications. A Flip Voltage Follower (FVF) circuit is used for the current tail to increase the current and increase the frequency bands. In this Schmitt-trigger delay changes associated with restructuring result in a 40 % power reduction. A circuit analysis for the equivalent circuit of the presented circuit has also been done and the factors affecting the frequency and delay change have been analyzed and investigated in the simulation. Monte Carlo and PVT analysis have also been performed for circuit accuracy. Power changing with an incremental delay in CMOS is improved and almost monotonous by designing Source-Coupled-Logic (SCL) Schmitt-trigger.