Unified functional decomposition via encoding for FPGA technology mapping

IF 3.1 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2001-04-01 DOI:10.1109/92.924031
Jie-Hong Jiang;Jing-Yang Jou;Juinn-Dar Huang
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引用次数: 5

Abstract

Functional decomposition has recently been adopted for look-up table (LUT)-based field-programmable gate array (FPGA) technology mapping with good results. In this paper we propose a novel method to unify functional single-output and multiple-output decomposition. We first address a compatible class encoding algorithm to minimize the number of compatible classes in the image function. After applying the encoding algorithm, we can therefore improve the decomposability in the subsequent decomposition of the image function. The above encoding algorithm is then extended to encode multiple-output functions through the construction of a hyperfunction. Common subexpressions among these multiple-output functions can be extracted during the decomposition of the hyperfunction. Consequently, we can handle multiple-output decomposition in the same manner as single-output decomposition. Experimental results show that our algorithms are promising.
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通过编码实现FPGA技术映射的统一功能分解
最近,基于查找表(LUT)的现场可编程门阵列(FPGA)技术映射采用了函数分解,取得了良好的效果。本文提出了一种统一函数单输出分解和多输出分解的新方法。我们首先提出了一种兼容类编码算法,以最小化图像函数中兼容类的数量。因此,在应用编码算法之后,我们可以在随后的图像函数分解中提高可分解性。然后,通过构造超函数,将上述编码算法扩展为对多个输出函数进行编码。可以在超函数的分解过程中提取这些多个输出函数之间的公共子表达式。因此,我们可以以与单输出分解相同的方式处理多输出分解。实验结果表明,我们的算法是有前景的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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