Signal-Strength Detector Based on CMOS-Inverter Supply Current

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Solid-State Circuits Letters Pub Date : 2023-08-22 DOI:10.1109/LSSC.2023.3307361

Pranav Kumar;Nagendra Krishnapura

引用次数: 0

Abstract

Pseudo-logarithmic signal-strength indicators are usually realized using a chain of amplifiers with amplitude detectors at the output of each stage and summing the output of the amplitude detectors. It is shown that the same can be achieved by measuring the total supply current of a pseudo-differential self-biased CMOS inverter chain. CMOS inverters act as amplifiers, and their supply current indicates the input amplitude. Amplification and amplitude detection are combined in the same block. The supply current is measured by mirroring the current in the pass transistor of the regulator that is used to power the inverter chain. The noise floor is set by the initial stages of the chain. A 65-nm prototype has a 70-dB dynamic range with ±1-dB error. It occupies 0.08

$\text {mm}^{{2}}$

and consumes 1.2 mW from 1.5V. The input referred noise floor is 0.2-mV rms.

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基于CMOS逆变电源电流的信号强度检测器

伪对数信号强度指示器通常使用在每一级的输出处具有幅度检测器的放大器链并将幅度检测器的输出求和来实现。结果表明，通过测量伪差分自偏置CMOS反相器链的总电源电流可以实现这一点。CMOS反相器充当放大器，其供电电流指示输入幅度。放大和幅度检测被组合在同一块中。电源电流是通过镜像用于为逆变器链供电的调节器的传输晶体管中的电流来测量的。噪声基底由链的初始阶段设置。65nm的原型具有70dB的动态范围，误差为±1-dB。它占用0.08$\text｛mm｝^｛2｝｝$，从1.5V消耗1.2 mW。输入参考噪声基底为0.2 mV rms。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量