E. Ray Hsieh;C. F. Huang;S. Y. Huang;M. L. Miu;S. M. Lu;Y. S. Wu;Y. H. Ye
{"title":"A Logic Fully Comparable Single-Supply Capacitor-Less 1-FinFET-1-Source-Channel-Drain-Diode (1T1D) Embedded DRAM MACRO in 16-nm FinFET","authors":"E. Ray Hsieh;C. F. Huang;S. Y. Huang;M. L. Miu;S. M. Lu;Y. S. Wu;Y. H. Ye","doi":"10.1109/LSSC.2023.3311797","DOIUrl":null,"url":null,"abstract":"We introduce one kind of embedded dynamic-random-access-memory (eDRAM) array (16 kilo-bits) with peripheral circuits. Each cell in an array comprises 1-control-Fin-type-field-effect-transistor [FinFET (T)] and 1-storage-npn-diode (D). The latter can be implemented by a nFinFET with the floating gate electrode. This 1T1D eDRAM technology is fully integrated with the 16-nm FinFET process and can be continually shrunk to the 3-nm technology node. The size of the unit-cell is \n<inline-formula> <tex-math>$0.0242~\\mu \\text{m}~^{\\mathrm{ 2}}$ </tex-math></inline-formula>\n. This 1T1D eDRAM cell can be programmed by the Zener-tunneling mechanism with 0.8 V of a writing voltage in 8 ns; the reading can be accomplished in 7 ns at −0.2 V. \n<inline-formula> <tex-math>$116~\\mu \\text{s}$ </tex-math></inline-formula>\n of data retention at 25°C (\n<inline-formula> <tex-math>$101~\\mu \\text{s}$ </tex-math></inline-formula>\n at 75°C); \n<inline-formula> <tex-math>$100~\\mu \\text{W}$ </tex-math></inline-formula>\n of the write power; \n<inline-formula> <tex-math>$9.125~\\mu \\text{W}$ </tex-math></inline-formula>\n of the read power have been recorded as well. These experimental pieces of evidence suggest that our 1T1D embedded DRAM technology could replace the conventional 1-transistor-1-capacitance (1T1C) eDRAM one with better cost-efficiency and lower power in the advanced CMOS technology to 3-nm node.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.2000,"publicationDate":"2023-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10243576/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
We introduce one kind of embedded dynamic-random-access-memory (eDRAM) array (16 kilo-bits) with peripheral circuits. Each cell in an array comprises 1-control-Fin-type-field-effect-transistor [FinFET (T)] and 1-storage-npn-diode (D). The latter can be implemented by a nFinFET with the floating gate electrode. This 1T1D eDRAM technology is fully integrated with the 16-nm FinFET process and can be continually shrunk to the 3-nm technology node. The size of the unit-cell is
$0.0242~\mu \text{m}~^{\mathrm{ 2}}$
. This 1T1D eDRAM cell can be programmed by the Zener-tunneling mechanism with 0.8 V of a writing voltage in 8 ns; the reading can be accomplished in 7 ns at −0.2 V.
$116~\mu \text{s}$
of data retention at 25°C (
$101~\mu \text{s}$
at 75°C);
$100~\mu \text{W}$
of the write power;
$9.125~\mu \text{W}$
of the read power have been recorded as well. These experimental pieces of evidence suggest that our 1T1D embedded DRAM technology could replace the conventional 1-transistor-1-capacitance (1T1C) eDRAM one with better cost-efficiency and lower power in the advanced CMOS technology to 3-nm node.