Defect Localization Approach for Wafer-to-Wafer Hybrid Bonding Interconnects

IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Semiconductor Manufacturing Pub Date : 2023-09-04 DOI:10.1109/TSM.2023.3311452
Kristof J. P. Jacobs;Eric Beyne
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Abstract

A high-resolution frontside fault isolation methodology for the analysis of wafer-to-wafer (W2W) hybrid bonding interconnects in three-dimensional integration is reported. The approach utilizes the visible light optical beam induced resistance change (VL-OBIRCH) method and incorporates a localized substrate removal technique, eliminating the need for a costly backside approach that requires a solid immersion lens. The top silicon substrate is removed using laser lithography and selective etching techniques, enabling the utilization of 405 nm excitation light for the VL-OBIRCH analysis. The validity of the methodology is demonstrated on W2W interconnect test structures with varying interconnect pitch and pad dimensions. The effectiveness of the proposed approach is confirmed through cross-sectional analysis.
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晶圆间混合键合互连的缺陷定位方法
本文报道了一种用于三维集成中晶对晶(W2W)杂化键合互连分析的高分辨率正面故障隔离方法。该方法利用可见光光束诱导电阻变化(VL-OBIRCH)方法,并结合了局部基板去除技术,消除了需要固体浸没透镜的昂贵的后侧方法的需要。使用激光光刻和选择性蚀刻技术去除顶部的硅衬底,使利用405 nm激发光进行VL-OBIRCH分析成为可能。在不同间距和焊盘尺寸的W2W互连测试结构上验证了该方法的有效性。通过横断面分析验证了该方法的有效性。
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来源期刊
IEEE Transactions on Semiconductor Manufacturing
IEEE Transactions on Semiconductor Manufacturing 工程技术-工程:电子与电气
CiteScore
5.20
自引率
11.10%
发文量
101
审稿时长
3.3 months
期刊介绍: The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components, especially very large scale integrated circuits (VLSI). Manufacturing these products requires precision micropatterning, precise control of materials properties, ultraclean work environments, and complex interactions of chemical, physical, electrical and mechanical processes.
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