An Efficient Architecture of Adder Using Fault-Tolerant Majority Gate Based on Atomic Silicon Nanotechnology

IF 2.1 4区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Nanotechnology Pub Date : 2023-08-29 DOI:10.1109/TNANO.2023.3309908
Seyed-Sajad Ahmadpour;Nima Jafari Navimipour;Ali Newaz Bahar;Senay Yalcin
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引用次数: 1

Abstract

It is expected that Complementary Metal Oxide Semiconductor (CMOS) implementation with ever-smaller transistors will soon face significant issues such as device density, power consumption, and performance due to the requirement for challenging fabrication processes. Therefore, a new and promising computation paradigm, nanotechnology, can replace CMOS technology. In addition, a new frontier in computing is opened up by nanotechnology called atomic silicon, which has the same extraordinary behavior as quantum dots. On the other hand, atomic silicon circuits are highly prone to defects, so suggested fault-tolerant structures in this technology play important roles. The full adders have gained popularity and find widespread use in efficiently solving mathematical problems. In the following article, we will explore the development of an efficient fault-tolerant 3-input majority gate (FT-MV3) using DBs, further enhancing the capabilities of digital circuits. A rule-based approach to the redundant DB achieves a less complex and more robust atomic silicon layout for the MV3. We use the SiQAD tool to simulate proposed circuits. In addition, to confirm the efficiency of the proposed gate, all common defects, such as single and double dangling bond omission defects and DB dislocation defects, are examined. The suggested gate is 100% and 66.66% tolerant against single and double DB omission defects, respectively. Furthermore, a new adder design is introduced using the suggested FT-MV3 gate. The results show that the suggested adder is 44.44% and 35.35% tolerant against single and double DB omission defects. Finally, a fault-tolerant four-bit adder is designed based on the proposed adder.
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基于原子硅纳米技术的高效容错多数门加法器结构
由于对具有挑战性的制造工艺的要求,预计具有更小晶体管的互补金属氧化物半导体(CMOS)实现将很快面临诸如器件密度、功耗和性能等重大问题。因此,一个新的和有前途的计算范式,纳米技术,可以取代CMOS技术。此外,被称为原子硅的纳米技术开辟了计算的新前沿,它具有与量子点相同的非凡行为。另一方面,原子硅电路极易产生缺陷,因此建议的容错结构在该技术中起着重要作用。全加法器在有效解决数学问题方面得到了广泛的应用。在下一篇文章中,我们将探讨使用db开发一种高效的容错三输入多数门(FT-MV3),进一步增强数字电路的功能。基于规则的冗余DB方法为MV3实现了不那么复杂和更健壮的原子硅布局。我们使用SiQAD工具来模拟所提出的电路。此外,为了验证所提出栅极的效率,对所有常见缺陷,如单双悬空键遗漏缺陷和DB位错缺陷进行了检查。所建议的栅极对单DB遗漏缺陷和双DB遗漏缺陷的容忍度分别为100%和66.66%。此外,还介绍了一种新的加法器设计,采用了建议的FT-MV3门。结果表明,该加法器对单、双DB遗漏缺陷的容忍度分别为44.44%和35.35%。最后,在此基础上设计了一个容错的四位加法器。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Transactions on Nanotechnology
IEEE Transactions on Nanotechnology 工程技术-材料科学:综合
CiteScore
4.80
自引率
8.30%
发文量
74
审稿时长
8.3 months
期刊介绍: The IEEE Transactions on Nanotechnology is devoted to the publication of manuscripts of archival value in the general area of nanotechnology, which is rapidly emerging as one of the fastest growing and most promising new technological developments for the next generation and beyond.
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