N. Pandey, Bharat Choudhary, K. Gupta, Ankit Mittal
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引用次数: 5
Abstract
This paper proposes new positive feedback source coupled logic (PFSCL) tristate buffers suited to bus applications. The proposed buffers use switch to attain high impedance state and modify the load or the current source section. An interesting consequence of this is overall reduction in the power consumption. The proposed tristate buffers consume half the power compared to the available switch based counterpart. The issues with available PFSCL tristate buffers based bus implementation are identified and benefits of employing the proposed tristate buffer topologies are put forward. SPICE simulation results using TSMC 180 nm CMOS technology parameters are included to support the theoretical formulations. The performance of proposed tristate buffer topologies is examined on the basis of propagation delay, output enable time, and power consumption. It is found that one of the proposed tristate buffer topology outperforms the others in terms of all the performance parameters. An examination of behavior of available and the proposed PFSCL tristate buffer topologies under parameter variations and mismatch shows a maximum variation of 14%.
期刊介绍:
Active and Passive Electronic Components is an international journal devoted to the science and technology of all types of electronic components. The journal publishes experimental and theoretical papers on topics such as transistors, hybrid circuits, integrated circuits, MicroElectroMechanical Systems (MEMS), sensors, high frequency devices and circuits, power devices and circuits, non-volatile memory technologies such as ferroelectric and phase transition memories, and nano electronics devices and circuits.