S. Roshani, Salah I. Yahya, Maher Assaad, Muhammad Akmal Chaudhary, F. Hazzazi, Yazeed Yasin Ghadi, Saeed Mostafaei, S. Roshani
In this paper, a compact and simple structure of an elliptic microstrip lowpass filter (LPF) is designed for harmonic suppression in microwave quadrature hybrid coupler (QHC) applications. A radial resonator and a rectangular resonator are used to produce an elliptic LPF. The proposed LPF is used on the outer sides of the branch line coupler, which has improved the coupler harmonic suppression. Furthermore, artificial neural networks (ANNs) are incorporated to improve the LPF design process. The LPF best structure is obtained using the proposed ANN model. The proposed LPF has a compact size, which only occupies 16.4 mm × 7.3 mm equals to 0.164 λg × 0.073 λg, has a cut frequency of 2.2 GHz, and shows a sharp transmission band with a roll-off rate of 158.3 dB/GHz. Finally, the deigned QHC operates correctly at 1 GHz, which shows high harmonic suppression ability. The proposed QHC provides wide suppression band from 2.25 GHz up to more than 14 GHz, which can effectively suppress 3rd, to 14th harmonics. The proposed coupler features desirable parameters of S11, S21, S31, and S41, with magnitude of −21 dB, −3.4 dB, −3.3 dB, and −22.5 dB, at the operating frequency. The proposed approach mitigates the complexity of the circuit fabrication, compared with the previous methods while achieved desirable performances for the proposed QHC.
{"title":"Design of a Microwave Quadrature Hybrid Coupler with Harmonic Suppression Using Artificial Neural Networks","authors":"S. Roshani, Salah I. Yahya, Maher Assaad, Muhammad Akmal Chaudhary, F. Hazzazi, Yazeed Yasin Ghadi, Saeed Mostafaei, S. Roshani","doi":"10.1155/2024/8722642","DOIUrl":"https://doi.org/10.1155/2024/8722642","url":null,"abstract":"In this paper, a compact and simple structure of an elliptic microstrip lowpass filter (LPF) is designed for harmonic suppression in microwave quadrature hybrid coupler (QHC) applications. A radial resonator and a rectangular resonator are used to produce an elliptic LPF. The proposed LPF is used on the outer sides of the branch line coupler, which has improved the coupler harmonic suppression. Furthermore, artificial neural networks (ANNs) are incorporated to improve the LPF design process. The LPF best structure is obtained using the proposed ANN model. The proposed LPF has a compact size, which only occupies 16.4 mm × 7.3 mm equals to 0.164 λg × 0.073 λg, has a cut frequency of 2.2 GHz, and shows a sharp transmission band with a roll-off rate of 158.3 dB/GHz. Finally, the deigned QHC operates correctly at 1 GHz, which shows high harmonic suppression ability. The proposed QHC provides wide suppression band from 2.25 GHz up to more than 14 GHz, which can effectively suppress 3rd, to 14th harmonics. The proposed coupler features desirable parameters of S11, S21, S31, and S41, with magnitude of −21 dB, −3.4 dB, −3.3 dB, and −22.5 dB, at the operating frequency. The proposed approach mitigates the complexity of the circuit fabrication, compared with the previous methods while achieved desirable performances for the proposed QHC.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2024-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140253475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wei Yao, Yang Liu, Lei Guo, Guojun Ding, Chaofeng Zhang, Sen Wang
For the difference of thyristor junction temperature at all levels in the transducer valve assembly in the series water circuit, an equivalent model of thyristor junction temperature calculation for the valve assembly is established, and PLECS simulation software is used to simulate and solve the junction temperature at all levels of the thyristor and check the junction temperature of the thyristor from the highest temperature of the measured radiator surface, and the results of the junction temperature checking show that the equivalent model of thyristor junction temperature calculation for the valve assembly has a high accuracy.
{"title":"Research on Equivalent Circuit Model of HVDC Valve and Calculation of Thyristor Junction Temperature","authors":"Wei Yao, Yang Liu, Lei Guo, Guojun Ding, Chaofeng Zhang, Sen Wang","doi":"10.1155/2024/6671153","DOIUrl":"https://doi.org/10.1155/2024/6671153","url":null,"abstract":"For the difference of thyristor junction temperature at all levels in the transducer valve assembly in the series water circuit, an equivalent model of thyristor junction temperature calculation for the valve assembly is established, and PLECS simulation software is used to simulate and solve the junction temperature at all levels of the thyristor and check the junction temperature of the thyristor from the highest temperature of the measured radiator surface, and the results of the junction temperature checking show that the equivalent model of thyristor junction temperature calculation for the valve assembly has a high accuracy.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2024-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140492918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study presents a dynamic amplifier with high energy efficiency and high gain suitable for a delta-sigma modulator based on the floating-inverter amplifier (FIA), in-depth analysis of the existing FIA and its improved structure, and simulation verification. Compared with other FIA structures, the proposed amplifier has a better compromise in terms of power consumption and stability, which was designed and simulated using the SMIC 180 nm CMOS technology. Under a 1.2 V power supply, the closed-loop direct current (DC) gain and the output swing were about 104 dB and ±380 mV, respectively, and the input-referred in-band noise was about −100 dB with the chopper circuit.
本研究基于浮动逆变放大器（FIA），深入分析了现有 FIA 及其改进结构，并进行了仿真验证，从而提出了一种适合三角积分调制器的高能效、高增益动态放大器。与其他 FIA 结构相比，所提出的放大器在功耗和稳定性方面具有更好的折衷效果，该放大器采用中芯国际 180 nm CMOS 技术进行设计和仿真。在 1.2 V 电源下，闭环直流增益和输出摆幅分别约为 104 dB 和 ±380 mV，使用斩波电路时输入参考带内噪声约为 -100 dB。
{"title":"Analysis and Design of High-Energy-Efficiency Amplifiers for Delta-Sigma Modulators","authors":"Jinze Lai, Yuxuan Lin, Gumeng Zhao, Lijie Huang, Cong Wei, Rongshan Wei, Wei Hu","doi":"10.1155/2023/2265990","DOIUrl":"https://doi.org/10.1155/2023/2265990","url":null,"abstract":"This study presents a dynamic amplifier with high energy efficiency and high gain suitable for a delta-sigma modulator based on the floating-inverter amplifier (FIA), in-depth analysis of the existing FIA and its improved structure, and simulation verification. Compared with other FIA structures, the proposed amplifier has a better compromise in terms of power consumption and stability, which was designed and simulated using the SMIC 180 nm CMOS technology. Under a 1.2 V power supply, the closed-loop direct current (DC) gain and the output swing were about 104 dB and ±380 mV, respectively, and the input-referred in-band noise was about −100 dB with the chopper circuit.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2023-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139246450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An improved method of extracting small-signal equivalent circuit model parameters for gallium nitride high electron mobility transistors (GaN HEMTs) is presented. This paper intends to present a method to extract the parasitic inductance and resistance of transistors based on the short-test structure without the open-circuit test structure. The parasitic capacitance of transistors is extracted by the method based on the size scalable model. Compared with the traditional COLD-FET method, the extraction procedure is simpler and more convenient. After removing the influence of parasitic elements, the intrinsic parameters of the model can be extracted by the S-parameters measured at different bias points. The experimental results show that the simulation results have good agreement with the measured results in the range of 0.5∼110 GHz.
本文介绍了一种提取氮化镓高电子迁移率晶体管（GaN HEMT）小信号等效电路模型参数的改进方法。本文旨在介绍一种基于短路测试结构而非开路测试结构来提取晶体管寄生电感和电阻的方法。该方法基于尺寸可扩展模型提取晶体管的寄生电容。与传统的 COLD-FET 方法相比，提取过程更加简单方便。在消除寄生元件的影响后，可以通过在不同偏置点测量的 S 参数来提取模型的内在参数。实验结果表明，在 0.5∼110 GHz 范围内，仿真结果与测量结果具有良好的一致性。
{"title":"An Ameliorated Small-Signal Model Parameter Extraction Method for GaN HEMTs up to 110 GHz with Short-Test Structure","authors":"Qingyu Yuan, Jinze Tang, Xiaodong Luan, Xin Lin, Fan Chang, Jiali Cheng","doi":"10.1155/2023/5589831","DOIUrl":"https://doi.org/10.1155/2023/5589831","url":null,"abstract":"An improved method of extracting small-signal equivalent circuit model parameters for gallium nitride high electron mobility transistors (GaN HEMTs) is presented. This paper intends to present a method to extract the parasitic inductance and resistance of transistors based on the short-test structure without the open-circuit test structure. The parasitic capacitance of transistors is extracted by the method based on the size scalable model. Compared with the traditional COLD-FET method, the extraction procedure is simpler and more convenient. After removing the influence of parasitic elements, the intrinsic parameters of the model can be extracted by the S-parameters measured at different bias points. The experimental results show that the simulation results have good agreement with the measured results in the range of 0.5∼110 GHz.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2023-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139251266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Uma Maheshwar Janniekode, Rajendra Prasad Somineni
With the percentage of embedded SRAM increasing in SoC chips, low-power design such as the near-threshold SRAM technique are getting increasing attention to reduce the entire chip energy consumption. However, the descending operating voltage will lead to longer write latency and a higher failure rate. In this paper, we present a novel low Vth ultradynamic voltage scaling (UDVS) 9T subthreshold SRAM cell to improve the write ability of SRAM cells. The proposed Low Vth UDVS SRAM cell is demonstrated with a low threshold voltage speed-up transistor and an ultradynamic voltage scaling circuit implemented in 16 nm low-leakage CMOS technology. This wide supply range was made possible by a combination of circuits optimized for both subthreshold and abovethreshold regimes. This write assist technique can be operated selectively to provide write capability at very low voltage levels while avoiding excessive power overhead. The simulation findings reveal that with 16 nm technology, the write ability is improved by 33% over the normal case at 0.9 V supply voltage.
{"title":"A Low Threshold Voltage Ultradynamic Voltage Scaling SRAM Write Assist Technique for High-Speed Applications","authors":"Uma Maheshwar Janniekode, Rajendra Prasad Somineni","doi":"10.1155/2023/1697836","DOIUrl":"https://doi.org/10.1155/2023/1697836","url":null,"abstract":"With the percentage of embedded SRAM increasing in SoC chips, low-power design such as the near-threshold SRAM technique are getting increasing attention to reduce the entire chip energy consumption. However, the descending operating voltage will lead to longer write latency and a higher failure rate. In this paper, we present a novel low Vth ultradynamic voltage scaling (UDVS) 9T subthreshold SRAM cell to improve the write ability of SRAM cells. The proposed Low Vth UDVS SRAM cell is demonstrated with a low threshold voltage speed-up transistor and an ultradynamic voltage scaling circuit implemented in 16 nm low-leakage CMOS technology. This wide supply range was made possible by a combination of circuits optimized for both subthreshold and abovethreshold regimes. This write assist technique can be operated selectively to provide write capability at very low voltage levels while avoiding excessive power overhead. The simulation findings reveal that with 16 nm technology, the write ability is improved by 33% over the normal case at 0.9 V supply voltage.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135539494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents the performance and stability analysis of the proposed built-in self-read and write assist 10T SRAM (BSRWA 10T) for better performance in terms of thermal stability and fast write access, which is suitable for military and aerospace applications. The performance of the proposed SRAM cell dominates the previous SRAM cells, i.e., conventional, fully differential 10T-ST (FD 10T-ST), single stacked disturbance-free 9T-ST (SSDF 9T-ST). The proposed SRAM cell dominates the SSDF 9T-ST SRAM cell in terms of write ability. The built-in self-read and write assist structure of the memory cell also dominates the improved write ability of SSDF 9T-ST SRAM by assist circuits such as negative bit line, ultra-dynamic voltage scaling (UDVS), write assist combining negative BL, and VDD collapse. The impact of assist circuits on write performance of memory cells is observed using Monte Carlo simulation for write margin (WM) parameter. WM of SSDF 9T-ST SRAM is improved by 15% and 25% by adding UDVS assist circuit and write assist combining negative BL and VDD collapse circuit. But BSRWA SRAM cell itself can improve WM by 32% without any assist circuit. The impact of temperature variation on the performance of memory cells is observed using Monte Carlo simulation for the HSNM parameter. The deviation of HSNM for 15°C to 55°C is 14%, 5%, 4%, and 1% in conventional SRAM cell, FD 10T SRAM cell, SSDF 9T SRAM cell, and proposed BSRWA 10T SRAM cell, respectively. The proposed SRAM cell is designed at a 22 nm CMOS technology node and verified in the Synopsys Custom compiler. MC simulation results are monitored on Synopsys Cosmo-scope wave viewer.
{"title":"Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell","authors":"Chokkakula Ganesh, Fazal Noorbasha","doi":"10.1155/2023/3371599","DOIUrl":"https://doi.org/10.1155/2023/3371599","url":null,"abstract":"This work presents the performance and stability analysis of the proposed built-in self-read and write assist 10T SRAM (BSRWA 10T) for better performance in terms of thermal stability and fast write access, which is suitable for military and aerospace applications. The performance of the proposed SRAM cell dominates the previous SRAM cells, i.e., conventional, fully differential 10T-ST (FD 10T-ST), single stacked disturbance-free 9T-ST (SSDF 9T-ST). The proposed SRAM cell dominates the SSDF 9T-ST SRAM cell in terms of write ability. The built-in self-read and write assist structure of the memory cell also dominates the improved write ability of SSDF 9T-ST SRAM by assist circuits such as negative bit line, ultra-dynamic voltage scaling (UDVS), write assist combining negative BL, and VDD collapse. The impact of assist circuits on write performance of memory cells is observed using Monte Carlo simulation for write margin (WM) parameter. WM of SSDF 9T-ST SRAM is improved by 15% and 25% by adding UDVS assist circuit and write assist combining negative BL and VDD collapse circuit. But BSRWA SRAM cell itself can improve WM by 32% without any assist circuit. The impact of temperature variation on the performance of memory cells is observed using Monte Carlo simulation for the HSNM parameter. The deviation of HSNM for 15°C to 55°C is 14%, 5%, 4%, and 1% in conventional SRAM cell, FD 10T SRAM cell, SSDF 9T SRAM cell, and proposed BSRWA 10T SRAM cell, respectively. The proposed SRAM cell is designed at a 22 nm CMOS technology node and verified in the Synopsys Custom compiler. MC simulation results are monitored on Synopsys Cosmo-scope wave viewer.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2023-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48168428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Combining with a static random-access memory (SRAM) and resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell is proposed in this study. With differential mode, a pair of 1T1R RRAM is added to 6T SRAM storage node. By optimizing the connection and layout scheme, the power consumption is reduced and the data stability is improved. The nvSRAM memory cell is realized with UMC CMOS 28 nm 1p9m process. When the power supply voltage is 0.9 V, the static noise/read/write margin is 0.35 V, 0.16 V, and 0.41 V, respectively. The data storage/restoration time is 0.21 ns and 0.18 ns, respectively, with an active area of 0.97 μm2.
{"title":"A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology Node","authors":"Jiayu Yin, W.-J. Liao, Chengying Chen","doi":"10.1155/2023/2364341","DOIUrl":"https://doi.org/10.1155/2023/2364341","url":null,"abstract":"Combining with a static random-access memory (SRAM) and resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell is proposed in this study. With differential mode, a pair of 1T1R RRAM is added to 6T SRAM storage node. By optimizing the connection and layout scheme, the power consumption is reduced and the data stability is improved. The nvSRAM memory cell is realized with UMC CMOS 28 nm 1p9m process. When the power supply voltage is 0.9 V, the static noise/read/write margin is 0.35 V, 0.16 V, and 0.41 V, respectively. The data storage/restoration time is 0.21 ns and 0.18 ns, respectively, with an active area of 0.97 μm2.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2023-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43834671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kawther I. Arafa, Dina M. Ellaithy, A. Zekry, M. Abouelatta, H. Shawkey
This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.
{"title":"Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications","authors":"Kawther I. Arafa, Dina M. Ellaithy, A. Zekry, M. Abouelatta, H. Shawkey","doi":"10.1155/2023/3669255","DOIUrl":"https://doi.org/10.1155/2023/3669255","url":null,"abstract":"This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2023-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64794172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
High-voltage gain converter has a high-frequency use in some industrial fields, for instance, the fuel cell system, the photovoltaic system, electric vehicles, and the high-intensity discharge lamp. In order to solve the problem of the low-voltage gain of traditional boost converter, the double-boost converter with coupled inductance and doubled voltage is proposed, which connects the traditional boost converter in parallel. The voltage gain of the converter is further improved by introducing the voltage-doubled unit of the coupled inductance. Moreover, the clamp capacitor can absorb the leakage inductance in the circuit and reduce the voltage stress of the switch. In addition, two coupled inductors are magnetically collected; then, the loss of the core is analyzed under the same gain. The detailed analysis of the proposed converter and a comparison considering other topologies previously published in the literature are also presented in this article. In order to verify the proposed converter performance, a prototype has been built for a power of 200 W, input and output voltages of 12 and 84 V, respectively, and a switching frequency of 50 kHz. Experimental results validate the effectiveness of the theoretical analysis proving the satisfactory converter performance, whose peak efficiency is 95.5%.
{"title":"A Double-Boost Converter Based on Coupled Inductance and Magnetic Integration","authors":"Hongzhu Li, Lingwei Zhu, Le Wang","doi":"10.1155/2021/8014620","DOIUrl":"https://doi.org/10.1155/2021/8014620","url":null,"abstract":"High-voltage gain converter has a high-frequency use in some industrial fields, for instance, the fuel cell system, the photovoltaic system, electric vehicles, and the high-intensity discharge lamp. In order to solve the problem of the low-voltage gain of traditional boost converter, the double-boost converter with coupled inductance and doubled voltage is proposed, which connects the traditional boost converter in parallel. The voltage gain of the converter is further improved by introducing the voltage-doubled unit of the coupled inductance. Moreover, the clamp capacitor can absorb the leakage inductance in the circuit and reduce the voltage stress of the switch. In addition, two coupled inductors are magnetically collected; then, the loss of the core is analyzed under the same gain. The detailed analysis of the proposed converter and a comparison considering other topologies previously published in the literature are also presented in this article. In order to verify the proposed converter performance, a prototype has been built for a power of 200 W, input and output voltages of 12 and 84 V, respectively, and a switching frequency of 50 kHz. Experimental results validate the effectiveness of the theoretical analysis proving the satisfactory converter performance, whose peak efficiency is 95.5%.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2021-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42146024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a new type of tri-input tunneling field-effect transistor (Ti-TFET) that can compactly realize the “Majority-Not” logic function with a single transistor. It features an ingenious T-shaped channel and three independent-biasing gates deposited and patterned on its left, right, and upper sides, which greatly enhance the electrostatic control ability between any two gates of all the three gates on the device channel and thus increase its turn-on current. The total current density and energy band distribution in different biasing conditions are analyzed in detail by TCAD simulations. The turn-on current, leakage current, and ratio of turn-on/off current are optimized by choosing appropriate work function and body thickness. TCAD simulation results verify the expected characteristics of the proposed Ti-TFETs in different working states. Ti-TFETs can flexibly be used to implement a logic circuit with a compact style and thus reduce the number of transistors and stack height of the circuits. It provides a new technique to reduce the chip area and power consumption by saving the number of transistors.
{"title":"A New Type of Tri-Input TFET with T-Shaped Channel Structure Exhibiting Three-Input Majority Logic Behavior","authors":"Ye Hao, Jiang Zhidi, Jianping Hu","doi":"10.1155/2021/8919283","DOIUrl":"https://doi.org/10.1155/2021/8919283","url":null,"abstract":"In this paper, we propose a new type of tri-input tunneling field-effect transistor (Ti-TFET) that can compactly realize the “Majority-Not” logic function with a single transistor. It features an ingenious T-shaped channel and three independent-biasing gates deposited and patterned on its left, right, and upper sides, which greatly enhance the electrostatic control ability between any two gates of all the three gates on the device channel and thus increase its turn-on current. The total current density and energy band distribution in different biasing conditions are analyzed in detail by TCAD simulations. The turn-on current, leakage current, and ratio of turn-on/off current are optimized by choosing appropriate work function and body thickness. TCAD simulation results verify the expected characteristics of the proposed Ti-TFETs in different working states. Ti-TFETs can flexibly be used to implement a logic circuit with a compact style and thus reduce the number of transistors and stack height of the circuits. It provides a new technique to reduce the chip area and power consumption by saving the number of transistors.","PeriodicalId":43355,"journal":{"name":"Active and Passive Electronic Components","volume":null,"pages":null},"PeriodicalIF":0.4,"publicationDate":"2021-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47880215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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