Enhancement of Data Retention Time in Dynamic Random Access Memory through Optimization of Sidewall Oxidation Precleaning (0.13 µm Tech 512 Mb)

Abstract

In this paper, we propose a dynamic random access memory (DRAM) data retention time enhancement method that minimizes silicon loss and undercut at the shallow trench isolation (STI) sidewall by reducing the standard cleaning 1 (SC1) time. SC1 time optimization mitigates the parasitic electric field in the STI's top corner, which reduces the inverse narrow width effect resulting in the reduction of channel doping density without increasing the subthreshold leakage of cell Transistor. Moreover, it minimizes the electric field in the depletion area from the cell junction to the P-well, thereby increasing yield or data retention time.