Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process

IF 1.3 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Active and Passive Electronic Components Pub Date : 2015-10-28 DOI:10.1155/2015/609828
A. Karsenty, A. Chelly
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引用次数: 1

Abstract

Nanoscale Gate-Recessed Channel (GRC) Fully Depleted- (FD-) SOI MOSFET device with a silicon channel thickness () as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K) for characterizations. In spite of its FD-SOI nanoscale thickness and long channel feature, the device has surprisingly exhibited a Drain-Induced Barrier Lowering (DIBL) effect at RT. However, this effect was suppressed at 77 K. If the apparition of such anomalous effect can be explained by a parasitic short channel transistor located at the edges of the channel, its suppression is explained by the decrease of the potential barrier between the drain and the channel when lowering the temperature.
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利用纳米栅极凹槽工艺研究完全耗尽SOI mosfet的异常DIBL效应
首先在室温下测试了硅沟道厚度()低至2.2 nm的纳米栅极凹槽(GRC)完全耗尽- (FD-) SOI MOSFET器件的功能检查,然后在低温(77 K)下进行了表征测试。尽管其FD-SOI具有纳米级厚度和长沟道特性,但该器件在室温下令人惊讶地表现出漏极诱导势垒降低(DIBL)效应。然而,这种效应在77 K时被抑制。如果这种异常效应的出现可以用位于沟道边缘的寄生短沟道晶体管来解释,那么它的抑制可以用降低温度时漏极和沟道之间的势垒降低来解释。
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来源期刊
Active and Passive Electronic Components
Active and Passive Electronic Components ENGINEERING, ELECTRICAL & ELECTRONIC-
CiteScore
1.30
自引率
0.00%
发文量
1
审稿时长
13 weeks
期刊介绍: Active and Passive Electronic Components is an international journal devoted to the science and technology of all types of electronic components. The journal publishes experimental and theoretical papers on topics such as transistors, hybrid circuits, integrated circuits, MicroElectroMechanical Systems (MEMS), sensors, high frequency devices and circuits, power devices and circuits, non-volatile memory technologies such as ferroelectric and phase transition memories, and nano electronics devices and circuits.
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