Siqiang Fan , He Tang , Hui Zhao , Xin Wang , Albert Wang , Bin Zhao , Gary G Zhang
{"title":"Enhanced Offset Averaging Technique for Flash ADC Design","authors":"Siqiang Fan , He Tang , Hui Zhao , Xin Wang , Albert Wang , Bin Zhao , Gary G Zhang","doi":"10.1016/S1007-0214(11)70041-4","DOIUrl":null,"url":null,"abstract":"<div><p>This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters (ADC). The new offset averaging design technique takes full advantage of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance and capacitance averaging factors to achieve maximum offset reduction in ADC designs. The new averaging method is verified in designing a 4 bit 1 Gs/s flash ADC that is implemented in foundry 0.13 μm CMOS technology.</p></div>","PeriodicalId":60306,"journal":{"name":"Tsinghua Science and Technology","volume":null,"pages":null},"PeriodicalIF":5.2000,"publicationDate":"2011-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/S1007-0214(11)70041-4","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Tsinghua Science and Technology","FirstCategoryId":"1093","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1007021411700414","RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"COMPUTER SCIENCE, INFORMATION SYSTEMS","Score":null,"Total":0}
引用次数: 12
Abstract
This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters (ADC). The new offset averaging design technique takes full advantage of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance and capacitance averaging factors to achieve maximum offset reduction in ADC designs. The new averaging method is verified in designing a 4 bit 1 Gs/s flash ADC that is implemented in foundry 0.13 μm CMOS technology.
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