{"title":"High level architectural synthesis: Precedence analysis and automatic cycle detection in data flow graphs","authors":"Anna Antola , Fausto Distante , Andrea Marches","doi":"10.1016/0165-6074(94)90020-5","DOIUrl":null,"url":null,"abstract":"<div><p>In this paper a low complexity procedure for precedence analysis and cycle detection in DFGs, representing abstract architectures during the high level synthesis process, is presented. The proposed approach aims to reduce the computational overhead required to take topological constraints into consideration during the scheduling process.</p></div>","PeriodicalId":100927,"journal":{"name":"Microprocessing and Microprogramming","volume":"40 10","pages":"Pages 693-696"},"PeriodicalIF":0.0000,"publicationDate":"1994-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/0165-6074(94)90020-5","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microprocessing and Microprogramming","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/0165607494900205","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper a low complexity procedure for precedence analysis and cycle detection in DFGs, representing abstract architectures during the high level synthesis process, is presented. The proposed approach aims to reduce the computational overhead required to take topological constraints into consideration during the scheduling process.
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