Efficient clocking of a wave-domino pipeline

Abstract

Wave pipelining is a technique used in digital systems for increased throughput. It is important to ensure the validity of the output signals, while increasing the rate at which data may be clocked into the pipeline. This is achieved by balancing the path delays from the inputs to all intermediate nodes and outputs. Wave-domino logic uses dynamic CMOS domino circuits to implement wave-pipelining. This paper builds upon existing work in wave-domino pipelining and introduces an improved clocking strategy for such a pipeline which further minimizes the clock period, thereby increasing the system throughput.