{"title":"Design of a direct digital synthesizer with an on-chip D/A-converter","authors":"J. Vankka, M. Waltari, M. Kosunen, K. Halonen","doi":"10.1109/ISCAS.1997.608504","DOIUrl":null,"url":null,"abstract":"A 140 MHz Direct Digital Synthesizer (DDS) with an on-chip D/A-converter is designed and processed in 0.8 /spl mu/m BiCMOS. The on-chip D/A-converter avoids delays and line loading caused by interchip connections. The frequency resolution of the DDS is 0.0326 Hz with a corresponding frequency switching speed of 150 ns. The digital parts of the chip are implemented with CMOS design in order to reduce power consumption. The D/A-converter is designed with BiCMOS technology to achieve 10 bit accuracy at a clock rate of 140 MHz. The chip has a complexity of 19,100 transistors with a die area of 12.2 mm/sup 2/. The simulated power dissipation is 0.58 W at 140 MHz.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"72 1","pages":"21-24 vol.1"},"PeriodicalIF":0.0000,"publicationDate":"1997-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"电路与系统学报","FirstCategoryId":"1093","ListUrlMain":"https://doi.org/10.1109/ISCAS.1997.608504","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
A 140 MHz Direct Digital Synthesizer (DDS) with an on-chip D/A-converter is designed and processed in 0.8 /spl mu/m BiCMOS. The on-chip D/A-converter avoids delays and line loading caused by interchip connections. The frequency resolution of the DDS is 0.0326 Hz with a corresponding frequency switching speed of 150 ns. The digital parts of the chip are implemented with CMOS design in order to reduce power consumption. The D/A-converter is designed with BiCMOS technology to achieve 10 bit accuracy at a clock rate of 140 MHz. The chip has a complexity of 19,100 transistors with a die area of 12.2 mm/sup 2/. The simulated power dissipation is 0.58 W at 140 MHz.