Reducing hardware complexity of motion estimation algorithms using truncated pixels

Abstract

Traditional block-matching motion estimation algorithms search motion vectors using full precision pixels, normally 8-bits-per-pixel. In this paper, we introduce an approach for block-matching motion estimation using truncated pixels. The full-search algorithm is employed for discussion. We investigate the system performance with different number of truncated bits. Simulation results show that the matching error decreases exponentially when the number of truncated bits is reduced, and the number of truncated bits of 4 can be chosen as a reasonable solution for motion vector searching. We also discovered that the average PSNR of the decoded video sequences degrades only 0.03%-2.1%, while the equivalent gate count drops 46% for many of the existing VLSI architectures!.