An optimized knight traversal technique to detect multiple faults and Module Sequence Graph based reconfiguration of microfluidic biochip

IF 1.1 4区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IET Computers and Digital Techniques Pub Date : 2020-12-16 DOI:10.1049/cdt2.12004
Basudev Saha, Mukta Majumder
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Abstract

Conventional biomedical analysers are replaced by digital microfluidic biochips and they are adequate to integrate different biomedical functions, essential for diverse bioassay operations. From the last decade, microfluidic biochips are getting plenty of acceptances in the field of miscellaneous healthcare sectors like DNA analysis, drug discovery and clinical diagnosis. These devices are also bearing a vital role in the area of safety critical applications such as food safety testing, air quality monitoring etc. As these devices are used in safety critical applications, clinical diagnosis and real-time biomolecular assay operations, these must have properties like precision, reliability and robustness. To accept it for discriminating purposes, the microfluidic device must endorse its preciseness and strength by following sublime testing strategy. Here, an optimized droplet traversal technique is proposed to investigate the multiple defective electrodes of a digital microfluidic biochip by embedding boundary cum row traversal and KNIGHT traversal procedure (based on the famous Knight Tour Problem). The proposed approach also enumerates the traversal time for a fault-free biochip. In addition to identifying the faulty electrodes, a Module Sequencing Graph based reconfiguration technique is proposed here to reinstate the device for normal bioassay operation.

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基于优化骑士遍历技术的多故障检测及模块序列图的微流控生物芯片重构
传统的生物医学分析仪被数字微流控生物芯片所取代,它们足以集成不同的生物医学功能,对于不同的生物分析操作至关重要。近十年来,微流控生物芯片在DNA分析、药物研发和临床诊断等医疗保健领域得到了广泛的应用。这些设备在食品安全检测、空气质量监测等安全关键应用领域也发挥着至关重要的作用。由于这些设备用于安全关键应用,临床诊断和实时生物分子分析操作,这些设备必须具有精度,可靠性和鲁棒性等特性。微流控装置必须遵循崇高的测试策略,以保证其准确性和强度,才能接受它的鉴别目的。本文提出了一种优化的液滴遍历技术,通过嵌入边界行遍历和KNIGHT遍历程序(基于著名的KNIGHT Tour问题)来研究数字微流控生物芯片的多个缺陷电极。该方法还列举了无故障生物芯片的遍历时间。除了识别故障电极外,本文还提出了一种基于模块测序图的重构技术,以恢复设备的正常生物测定操作。
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来源期刊
IET Computers and Digital Techniques
IET Computers and Digital Techniques 工程技术-计算机:理论方法
CiteScore
3.50
自引率
0.00%
发文量
12
审稿时长
>12 weeks
期刊介绍: IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.
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