Design of faster & power efficient sense amplifier using VLSI technology

A. Pathrikar, R. Deshpande
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引用次数: 8

Abstract

In this paper we have designed Faster & Power Efficient Sense Amplifier for CMOS SRAM using VLSI Technology i.e. primarily schematic of sense amplifier is designed & simulated using ADS (Advanced Design System). The sense amplifier then implemented & analyzed at chip level using Microwind 3.1- a layout editor. The 45 nm & 32 nm technologies are used to analyze performance of Sense Amplifier. Our focus will be to reduce the size, to improve the power consumption and also to improve the response time of sense amplifier.
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利用VLSI技术设计更快、更节能的感测放大器
在本文中,我们利用VLSI技术为CMOS SRAM设计了更快、更节能的感测放大器,即使用ADS (Advanced Design System)设计和模拟了感测放大器的主要原理图。然后使用Microwind 3.1(一个布局编辑器)在芯片级实现和分析了该传感器放大器。采用45纳米和32纳米技术分析了感测放大器的性能。我们的重点将是缩小尺寸,提高功耗,并提高感测放大器的响应时间。
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