Kenichi Maruko, Tatsuya Sugioka, H. Hayashi, Zhiwei Zhou, Yasunori Tsukuda, Y. Yagishita, H. Konishi, Toshikyuki Ogata, Hisashi Owa, T. Niki, K. Konda, M. Sato, Hiroshi Shiroshita, Takeshi Ogura, T. Aoki, H. Kihara, Sachiya Tanaka
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引用次数: 34
Abstract
Since the I/O bandwidth demand for mobile consumer electronics has been growing rapidly, the importance of high-speed low-power I/O links has also been increasing. Among proposed I/O architectures, [1] and [2] are attractive solutions. However, for an application that needs the burst-mode operation, the lock-in time should be within the period of several tens of bits. Therefore, the PLL-based phase rotator with a longer lock-in time, is not suitable for this purpose. In this paper, a 1.296-to-5.184Gb/s transceiver uses an injection-locking-based CDR. The proposed CDR architecture, dual-edge injection-locked oscillator CDR (DILO-CDR), realizes fast lock (≪20 bits), continuous-rate capability (1.296 to 5.184Gb/s) and 2× power efficiency [2.4mW/(Gb/s)] of previous fast-lock continuous-rate CDRs [3, 4].
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