Pub Date : 2010-03-22DOI: 10.1109/ISSCC.2010.5434720
Dongmyung Lee, Jung-Won Han, E. Chang, G. Han, Sung Min Park
Recently, low-cost silicon optoelectronic integrated circuits (OEICs) have been drawing attention for applications in short-distance optical communications such as chip-to-chip and board-to-board interconnects, LAN, data storage networks, etc [1–4]. Particularly, single-chip OEICs with on-chip silicon photodiodes provide a number of advantages including low cost, reduced ground-bounce, and bond-wire-induced coupling. Nevertheless, the slow response of silicon photodiodes in a standard CMOS process serves as a major bottleneck for high-speed communication [1]. To improve the bandwidth of silicon photodiodes, either some process modification or avalanche photodiode implementation has been developed. However, the former results in increased costs, whereas the latter has reliability issues. Although a differential photodiode configuration was originally proposed for bandwidth extension [2–4], the operation speed is still limited to several-hundred Mb/s. Meanwhile, the bandwidth can be extended by exploiting equalization filter [1, 3]. For relatively low-Gb/s operations, fixed equalization filter is sufficient, because photodiode responsivity is dominantly determined by diffusion currents which are not sensitive to process and temperature variations. For higher speeds, the responsivity becomes strongly dependent on the process and temperature variations, because it is mainly determined by the carrier mobility. Thereby, equalizers for high-Gb/s optical receivers require an adaptation algorithm to compensate the significant process and temperature variations. In this paper, an OEIC with on-chip photodiode is presented. Bandwidth and responsivity are compensated by a compact adaptive equalizer, thus achieving 8.5Gb/s operation.
{"title":"An 8.5Gb/s CMOS OEIC with on-chip photodiode for short-distance optical communications","authors":"Dongmyung Lee, Jung-Won Han, E. Chang, G. Han, Sung Min Park","doi":"10.1109/ISSCC.2010.5434720","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434720","url":null,"abstract":"Recently, low-cost silicon optoelectronic integrated circuits (OEICs) have been drawing attention for applications in short-distance optical communications such as chip-to-chip and board-to-board interconnects, LAN, data storage networks, etc [1–4]. Particularly, single-chip OEICs with on-chip silicon photodiodes provide a number of advantages including low cost, reduced ground-bounce, and bond-wire-induced coupling. Nevertheless, the slow response of silicon photodiodes in a standard CMOS process serves as a major bottleneck for high-speed communication [1]. To improve the bandwidth of silicon photodiodes, either some process modification or avalanche photodiode implementation has been developed. However, the former results in increased costs, whereas the latter has reliability issues. Although a differential photodiode configuration was originally proposed for bandwidth extension [2–4], the operation speed is still limited to several-hundred Mb/s. Meanwhile, the bandwidth can be extended by exploiting equalization filter [1, 3]. For relatively low-Gb/s operations, fixed equalization filter is sufficient, because photodiode responsivity is dominantly determined by diffusion currents which are not sensitive to process and temperature variations. For higher speeds, the responsivity becomes strongly dependent on the process and temperature variations, because it is mainly determined by the carrier mobility. Thereby, equalizers for high-Gb/s optical receivers require an adaptation algorithm to compensate the significant process and temperature variations. In this paper, an OEIC with on-chip photodiode is presented. Bandwidth and responsivity are compensated by a compact adaptive equalizer, thus achieving 8.5Gb/s operation.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74271479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433922
J. Tschanz, K. Bowman, Shih-Lien Lu, Paolo A. Aseron, M. Khellah, A. Raychowdhury, B. Geuskens, Carlos Tokunaga, C. Wilkerson, T. Karnik, V. De
Microprocessors experience a wide range of dynamic variations, including voltage droops, temperature changes, and device aging, which vary across applications and systems. The necessity of ensuring correct operation even under infrequent worst-case conditions results in clock frequency (FCLK) or supply voltage (VCC) guardbands that degrade performance and increase energy consumption. In this paper, a research microprocessor core is described with resilient and adaptive circuits to mitigate dynamic variation guardbands for maximizing throughput or minimizing energy. The resiliency features consist of embedded error-detection sequentials (EDS) [1-4] and tunable replica circuits (TRC) [5] in conjunction with error-recovery circuits to detect and correct timing errors. A new instruction-replay error-recovery technique is introduced to correct errant instructions with low performance cost and implementation overhead. In addition, the microprocessor contains an adaptive clock controller based on error statistics to operate at maximum efficiency across a range of dynamic variations.
{"title":"A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance","authors":"J. Tschanz, K. Bowman, Shih-Lien Lu, Paolo A. Aseron, M. Khellah, A. Raychowdhury, B. Geuskens, Carlos Tokunaga, C. Wilkerson, T. Karnik, V. De","doi":"10.1109/ISSCC.2010.5433922","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433922","url":null,"abstract":"Microprocessors experience a wide range of dynamic variations, including voltage droops, temperature changes, and device aging, which vary across applications and systems. The necessity of ensuring correct operation even under infrequent worst-case conditions results in clock frequency (FCLK) or supply voltage (VCC) guardbands that degrade performance and increase energy consumption. In this paper, a research microprocessor core is described with resilient and adaptive circuits to mitigate dynamic variation guardbands for maximizing throughput or minimizing energy. The resiliency features consist of embedded error-detection sequentials (EDS) [1-4] and tunable replica circuits (TRC) [5] in conjunction with error-recovery circuits to detect and correct timing errors. A new instruction-replay error-recovery technique is introduced to correct errant instructions with low performance cost and implementation overhead. In addition, the microprocessor contains an adaptive clock controller based on error statistics to operate at maximum efficiency across a range of dynamic variations.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78387240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433843
T. Tokairin, Mitsuji Okada, M. Kitsunezuka, T. Maeda, M. Fukaishi
All-digital phase-locked loops (ADPLLs) offer the advantages of eliminating the large on-chip passive filter and not suffering from poor low-supply-voltage operation with process scaling [1,2]. However, there is a challenge in achieving low power consumption at the same time as providing the low phase noise required in modern wireless systems like WiFi and WiMAX that have higher-order modulations. Recently, efforts improve phase noise have been accomplished by increasing the time resolution of the time-to-digital converter (TDC) using a gated ring-oscillator structure by using a multipath ring oscillator [3], 2-step structures based on a vernier delay line [4] or a time-amplifier [5,6]. However, these structures require large power consumption because they require many continuously operating high-speed delay-stages.
{"title":"A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC","authors":"T. Tokairin, Mitsuji Okada, M. Kitsunezuka, T. Maeda, M. Fukaishi","doi":"10.1109/ISSCC.2010.5433843","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433843","url":null,"abstract":"All-digital phase-locked loops (ADPLLs) offer the advantages of eliminating the large on-chip passive filter and not suffering from poor low-supply-voltage operation with process scaling [1,2]. However, there is a challenge in achieving low power consumption at the same time as providing the low phase noise required in modern wireless systems like WiFi and WiMAX that have higher-order modulations. Recently, efforts improve phase noise have been accomplished by increasing the time resolution of the time-to-digital converter (TDC) using a gated ring-oscillator structure by using a multipath ring oscillator [3], 2-step structures based on a vernier delay line [4] or a time-amplifier [5,6]. However, these structures require large power consumption because they require many continuously operating high-speed delay-stages.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78444301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434061
K. Raczkowski, W. Raedt, B. Nauwelaers, P. Wambacq
For high-data-rate wireless communication in the 7GHz band around 60GHz, the IEEE 802.15.3c standard [1] provides channels with a 0.88GHz bandwidth for the AV-OFDM mode. For the single-carrier modes, the ECMA 387 standard [2] foresees the possibility of bonding together adjacent channels, yielding higher data-rates. Radios for these 60GHz standards often use phased antenna arrays to relax the link budget. A phased-array receiver needs a variable phase shift on each antenna path and a combiner that sums the signals from the individual paths after phase shifting. The beamforming circuitry presented here handles 4 paths. It can operate both with one 0.88GHz channel and with bonding of two such channels. Phase shifts are realized with a resolution better than 20°. Bandwidth is high thanks to the use of current amplifiers with very low input impedance.
{"title":"A wideband beamformer for a phased-array 60GHz receiver in 40nm digital CMOS","authors":"K. Raczkowski, W. Raedt, B. Nauwelaers, P. Wambacq","doi":"10.1109/ISSCC.2010.5434061","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434061","url":null,"abstract":"For high-data-rate wireless communication in the 7GHz band around 60GHz, the IEEE 802.15.3c standard [1] provides channels with a 0.88GHz bandwidth for the AV-OFDM mode. For the single-carrier modes, the ECMA 387 standard [2] foresees the possibility of bonding together adjacent channels, yielding higher data-rates. Radios for these 60GHz standards often use phased antenna arrays to relax the link budget. A phased-array receiver needs a variable phase shift on each antenna path and a combiner that sums the signals from the individual paths after phase shifting. The beamforming circuitry presented here handles 4 paths. It can operate both with one 0.88GHz channel and with bonding of two such channels. Phase shifts are realized with a resolution better than 20°. Bandwidth is high thanks to the use of current amplifiers with very low input impedance.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75920638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433996
D. Fick, Nurrachman Liu, Z. Foo, Matthew R. Fojtik, Jae-sun Seo, D. Sylvester, D. Blaauw
Advanced CMOS technologies have become highly susceptible to process, voltage, and temperature (PVT) variation. The standard approach for addressing this issue is to increase timing margin at the expense of power and performance. One approach to reclaim these losses relies on canary circuits [1] or sensors [2], which are simple to implement but cannot account for local variations. A more recent approach, called Razor, uses delay speculation coupled with error detection and correction to remove all margins but also imposes significant design complexity [3]. In this paper, we present a minimally-invasive in situ delay slack monitor that directly measures the timing margins on critical timing signals, allowing margins due to both global and local PVT variations to be removed.
{"title":"In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter","authors":"D. Fick, Nurrachman Liu, Z. Foo, Matthew R. Fojtik, Jae-sun Seo, D. Sylvester, D. Blaauw","doi":"10.1109/ISSCC.2010.5433996","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433996","url":null,"abstract":"Advanced CMOS technologies have become highly susceptible to process, voltage, and temperature (PVT) variation. The standard approach for addressing this issue is to increase timing margin at the expense of power and performance. One approach to reclaim these losses relies on canary circuits [1] or sensors [2], which are simple to implement but cannot account for local variations. A more recent approach, called Razor, uses delay speculation coupled with error detection and correction to remove all margins but also imposes significant design complexity [3]. In this paper, we present a minimally-invasive in situ delay slack monitor that directly measures the timing margins on critical timing signals, allowing margins due to both global and local PVT variations to be removed.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77410355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433993
Jae-sun Seo, R. Ho, J. Lexau, Michael Dayringer, D. Sylvester, D. Blaauw
Long on-chip wires pose well-known latency, bandwidth, and energy challenges to the designers of high-performance VLSI systems. Repeaters effectively mitigate wire RC effects but do little to improve their energy costs. Moreover, proliferating repeater farms add significant complexity to full-chip integration, motivating circuits to improve wire performance and energy while reducing the number of repeaters. Such methods include capacitive-mode signaling, which combines a capacitive driver with a capacitive load [1,2]; and current-mode signaling, which pairs a resistive driver with a resistive load [3,4]. While both can significantly improve wire performance, capacitive drivers offer added benefits of reduced voltage swing on the wire and intrinsic driver pre-emphasis. As wires scale, slow slew rates on highly resistive interconnects will still limit wire performance due to inter-symbol interference (ISI) [5]. Further improvements can come from equalization circuits on receivers [2] and transmitters [4] that trade off power for bandwidth. In this paper, we extend these ideas to a capacitively driven pulse-mode wire using a transmit-side adaptive FIR filter and a clockless receiver, and show bandwidth densities of 2.2–4.4 Gb/s/µm over 90nm 5mm links, with corresponding energies of 0.24–0.34 pJ/bit on random data.
{"title":"High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS","authors":"Jae-sun Seo, R. Ho, J. Lexau, Michael Dayringer, D. Sylvester, D. Blaauw","doi":"10.1109/ISSCC.2010.5433993","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433993","url":null,"abstract":"Long on-chip wires pose well-known latency, bandwidth, and energy challenges to the designers of high-performance VLSI systems. Repeaters effectively mitigate wire RC effects but do little to improve their energy costs. Moreover, proliferating repeater farms add significant complexity to full-chip integration, motivating circuits to improve wire performance and energy while reducing the number of repeaters. Such methods include capacitive-mode signaling, which combines a capacitive driver with a capacitive load [1,2]; and current-mode signaling, which pairs a resistive driver with a resistive load [3,4]. While both can significantly improve wire performance, capacitive drivers offer added benefits of reduced voltage swing on the wire and intrinsic driver pre-emphasis. As wires scale, slow slew rates on highly resistive interconnects will still limit wire performance due to inter-symbol interference (ISI) [5]. Further improvements can come from equalization circuits on receivers [2] and transmitters [4] that trade off power for bandwidth. In this paper, we extend these ideas to a capacitively driven pulse-mode wire using a transmit-side adaptive FIR filter and a clockless receiver, and show bandwidth densities of 2.2–4.4 Gb/s/µm over 90nm 5mm links, with corresponding energies of 0.24–0.34 pJ/bit on random data.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77467318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433834
David Garner, Hua Bai, P. Georgiou, T. Constandinou, Samuel Reed, L. Shepherd, Winston Wong, K. T. Lim, C. Toumazou
Point-of-care diagnostics for detection of genetic sequences require biosensing platforms that are sensitive to the target sequence, and are also fast, mass-manufacturable, and - ideally - disposable. Conventional lab-based methods of detecting DNA sequences rely on optical methods, typically by the addition of fluorescent tags to the target DNA that in turn latches onto a DNA probe sequence only if there is a match between the two. These techniques are cumbersome as they require upfront tagging of the DNA with expensive reagents and laboratory equipment to detect the optical signals. Recently, developments have been made in transferring these optical methods to inexpensive CMOS ICs [1], although the requirement for tagging remains. Magnetic beads offer an alternative means of tagging the DNA and their presence can be detected by the shift in resonant frequency of an on-chip LC tank [2]. There have also been attempts based on “label-free” electrochemical detection using FETs [3,4], but none of these have been implemented in unmodified standard CMOS.
{"title":"A multichannel DNA SoC for rapid point-of-care gene detection","authors":"David Garner, Hua Bai, P. Georgiou, T. Constandinou, Samuel Reed, L. Shepherd, Winston Wong, K. T. Lim, C. Toumazou","doi":"10.1109/ISSCC.2010.5433834","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433834","url":null,"abstract":"Point-of-care diagnostics for detection of genetic sequences require biosensing platforms that are sensitive to the target sequence, and are also fast, mass-manufacturable, and - ideally - disposable. Conventional lab-based methods of detecting DNA sequences rely on optical methods, typically by the addition of fluorescent tags to the target DNA that in turn latches onto a DNA probe sequence only if there is a match between the two. These techniques are cumbersome as they require upfront tagging of the DNA with expensive reagents and laboratory equipment to detect the optical signals. Recently, developments have been made in transferring these optical methods to inexpensive CMOS ICs [1], although the requirement for tagging remains. Magnetic beads offer an alternative means of tagging the DNA and their presence can be detected by the shift in resonant frequency of an on-chip LC tank [2]. There have also been attempts based on “label-free” electrochemical detection using FETs [3,4], but none of these have been implemented in unmodified standard CMOS.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80141852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434067
G. Delagi
The mobile-handset market continues to be a dynamic and growing one, enabled by technology advances that include increased bandwidth, greater processing performance, increased power efficiency, and improved display technologies to deliver compelling user experiences. We envision a world in five years where mobile devices will offer new high-performance services and features, support always-on/always-aware connectivity, and deliver battery life that will provide days of active-use experience. These “smart mobile companion” devices of the future will be intelligent autonomous systems with a multitude of incorporated sensors and display options, all designed to make our lives easier and more productive.
{"title":"Harnessing technology to advance the next-generation mobile user-experience","authors":"G. Delagi","doi":"10.1109/ISSCC.2010.5434067","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434067","url":null,"abstract":"The mobile-handset market continues to be a dynamic and growing one, enabled by technology advances that include increased bandwidth, greater processing performance, increased power efficiency, and improved display technologies to deliver compelling user experiences. We envision a world in five years where mobile devices will offer new high-performance services and features, support always-on/always-aware connectivity, and deliver battery life that will provide days of active-use experience. These “smart mobile companion” devices of the future will be intelligent autonomous systems with a multitude of incorporated sensors and display options, all designed to make our lives easier and more productive.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81526027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433985
H. Ahmad, B. Bakkaloglu
Digitally controlled DC-DC converters enable design portability as well as reconfigurable compensation and control schemes. Digital controllers are also resistant to process and temperature variations making them attractive for SoC applications. The main building blocks of a digital controller for integrated switch-mode converters are the feedback ADC that digitizes the error signal, the digital compensator, and the digital PWM generator (DPWM). The ADC and DPWM blocks are typically the most challenging circuits to design in terms of power consumption, complexity, and area.
{"title":"A 300mA 14mV-ripple digitally controlled buck converter using frequency domain ΔΣ ADC and hybrid PWM generator","authors":"H. Ahmad, B. Bakkaloglu","doi":"10.1109/ISSCC.2010.5433985","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433985","url":null,"abstract":"Digitally controlled DC-DC converters enable design portability as well as reconfigurable compensation and control schemes. Digital controllers are also resistant to process and temperature variations making them attractive for SoC applications. The main building blocks of a digital controller for integrated switch-mode converters are the feedback ADC that digitizes the error signal, the digital compensator, and the digital PWM generator (DPWM). The ADC and DPWM blocks are typically the most challenging circuits to design in terms of power consumption, complexity, and area.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85072946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434077
J. Howard, S. Dighe, Y. Hoskote, S. Vangal, D. Finan, G. Ruhl, D. Jenkins, H. Wilson, N. Borkar, G. Schrom, Fabric Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, V. Erraguntla, M. Konow, Michael Riepen, G. Droege, Joerg Lindemann, M. Gries, T. Apel, K. Henriss, Tor Lund-Larsen, Sebastian Steibl, S. Borkar, V. De, R. V. D. Wijngaart, T. Mattson
Current developments in microprocessor design favor increased core counts over frequency scaling to improve processor performance and energy efficiency. Coupling this architectural trend with a message-passing protocol helps realize a data-center-on-a-die. The prototype chip (Figs. 5.7.1 and 5.7.7) described in this paper integrates 48 Pentium™ class IA-32 cores [1] on a 6×4 2D-mesh network of tiled core clusters with high-speed I/Os on the periphery. The chip contains 1.3B transistors. Each core has a private 256KB L2 cache (12MB total on-die) and is optimized to support a message-passing-programming model whereby cores communicate through shared memory. A 16KB message-passing buffer (MPB) is present in every tile, giving a total of 384KB on-die shared memory, for increased performance. Power is kept at a minimum by transmitting dynamic, fine-grained voltage-change commands over the network to an on-die voltage-regulator controller (VRC). Further power savings are achieved through active frequency scaling at the tile granularity. Memory accesses are distributed over four on-die DDR3 controllers for an aggregate peak memory bandwidth of 21GB/s at 4× burst. Additionally, an 8-byte bidirectional system interface (SIF) provides 6.4GB/s of I/O bandwidth. The die area is 567mm2 and is implemented in 45nm high-к metal-gate CMOS [2].
{"title":"A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS","authors":"J. Howard, S. Dighe, Y. Hoskote, S. Vangal, D. Finan, G. Ruhl, D. Jenkins, H. Wilson, N. Borkar, G. Schrom, Fabric Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, V. Erraguntla, M. Konow, Michael Riepen, G. Droege, Joerg Lindemann, M. Gries, T. Apel, K. Henriss, Tor Lund-Larsen, Sebastian Steibl, S. Borkar, V. De, R. V. D. Wijngaart, T. Mattson","doi":"10.1109/ISSCC.2010.5434077","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434077","url":null,"abstract":"Current developments in microprocessor design favor increased core counts over frequency scaling to improve processor performance and energy efficiency. Coupling this architectural trend with a message-passing protocol helps realize a data-center-on-a-die. The prototype chip (Figs. 5.7.1 and 5.7.7) described in this paper integrates 48 Pentium™ class IA-32 cores [1] on a 6×4 2D-mesh network of tiled core clusters with high-speed I/Os on the periphery. The chip contains 1.3B transistors. Each core has a private 256KB L2 cache (12MB total on-die) and is optimized to support a message-passing-programming model whereby cores communicate through shared memory. A 16KB message-passing buffer (MPB) is present in every tile, giving a total of 384KB on-die shared memory, for increased performance. Power is kept at a minimum by transmitting dynamic, fine-grained voltage-change commands over the network to an on-die voltage-regulator controller (VRC). Further power savings are achieved through active frequency scaling at the tile granularity. Memory accesses are distributed over four on-die DDR3 controllers for an aggregate peak memory bandwidth of 21GB/s at 4× burst. Additionally, an 8-byte bidirectional system interface (SIF) provides 6.4GB/s of I/O bandwidth. The die area is 567mm2 and is implemented in 45nm high-к metal-gate CMOS [2].","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83576607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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