Analytical thermal placement for VLSI lifetime improvement and minimum performance variation

Abstract

DSM and nanometer VLSI designs are subject to an increasingly significant thermal effect on VLSI circuit lifetime and performance variation, which can be effectively subdued by VLSI placement. We propose analytical placement for accurate and efficient VLSI thermal optimization, and propose minimized maximum on-chip temperature as the thermal optimization objective for improved VLSI lifetime and minimized performance variation. We develop an effective analytical thermal placement technique, as well as an improved analytical placement technique with a new cell spreading function. Our experimental results show that our proposed analytical thermal placement achieves 17.85% and 30.77% maximum on-chip temperature variation reduction as well as 4.61% and 0.45% wirelength reduction respectively for the two industry design test cases compared with thermal-oblivious analytical placement, e.g., APlace.