{"title":"A HARDWARE ACCELERATOR FOR THE COMPUTATION OF MODIFIED DISCRETE SINE TRANSFORM","authors":"D. Chiper","doi":"10.56082/annalsarsciinfo.2021.1-2.57","DOIUrl":null,"url":null,"abstract":"This work presents an efficient hardware implementation of a hardware accelerator for the computation of the Modified Discrete Sine transform (MDST) using a new VLSI algorithm based on a appropriate reformulation of the MDST algorithm using some auxiliary input and output sequences. The obtained hardware implementation is using a low complexity implementation based on only adders/subtracters and has a reduced critical path that can be exploited to obtain a significant reduction of the power consumption.","PeriodicalId":32445,"journal":{"name":"Annals Series on History and Archaeology Academy of Romanian Scientists","volume":"9 1","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Annals Series on History and Archaeology Academy of Romanian Scientists","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.56082/annalsarsciinfo.2021.1-2.57","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This work presents an efficient hardware implementation of a hardware accelerator for the computation of the Modified Discrete Sine transform (MDST) using a new VLSI algorithm based on a appropriate reformulation of the MDST algorithm using some auxiliary input and output sequences. The obtained hardware implementation is using a low complexity implementation based on only adders/subtracters and has a reduced critical path that can be exploited to obtain a significant reduction of the power consumption.
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