Design on ESD robustness of source-side discrete distribution in the 60-V high-voltage nLDMOS devices

Abstract

The electrostatic-discharge (ESD) protection capability of HV nLDMOS devices with the source-side engineering by a TSMC 0.25μm 60-V is investigated in this paper. It can be found that a pure nLDMOS device has a poor anti-ESD ability (It2 = 1.833A). At the same time, if an nLDMOS was embedded with an SCR npn-(pnp-) arranged type in the drain-side, the corresponding secondary breakdown-current values are promoted 19.4% (24.8%) as comparing with a traditional nLDMOS. Furthermore, if the source discrete methodology is applied for the nLDMOS-embedded SCR npn-(pnp-) arranged type, the maximum secondary breakdown current value are promoted 24.1% (>281.9%). Finally, it can be concluded that a discrete distribution in the source region of a pure nLDMOS will upgrade the anti-ESD capability effectively, and it is especially for the nLDMOS-SCR pnp-arranges type.