A 0.06mm2 8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOS

Abstract

In 10b SAR ADCs, one of the major design challenges is the large number of capacitors for implementing the capacitor array. A large unit capacitance should be used due to the design constraint of capacitor mismatches and/or layout design rules. As a result, the total capacitance is typically much larger than what is required by kT/C noise. In [1], a 10-bit SAR ADC is presented that achieves an area of 0.075mm2 with a charge redistribution architecture using a small unit capacitance of 10fF, while SNDR is low becasue of using such a small unit capacitance. The charge-sharing SAR proposed in [2] allows a relatively large unit capacitance by reducing the required number of capacitors. However, it requires a large (10pF) S/H capacitor for precise operation. The ADC presented in [3] needs large logic circuits to implement a complex calibration. The converter presented in [4] is a pipelined ADC. The pipelined architecture overcomes the unit capacitance issue of SAR, but the area and the power consumption of the amplifiers are still large.