{"title":"A I0-bit, 100 MS/s CMOS A/D Converter","authors":"K. Y. Kim, N. Kusayanagi, A. Abidi","doi":"10.1109/CICC.1996.510588","DOIUrl":null,"url":null,"abstract":"This work addresses some of the known problems inherent in time-interleaved, or parallel, ADCs with a new architecture. A prototype of this architecture demonstrates, for the first time, 10-bit operation at 100 MS/s in a 1 /spl mu/m CMOS technology.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"9 1","pages":"419-422"},"PeriodicalIF":0.0000,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1996.510588","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14
Abstract
This work addresses some of the known problems inherent in time-interleaved, or parallel, ADCs with a new architecture. A prototype of this architecture demonstrates, for the first time, 10-bit operation at 100 MS/s in a 1 /spl mu/m CMOS technology.
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