Pub Date : 2020-03-01Epub Date: 2020-04-23DOI: 10.1109/CICC48029.2020.9075888
Jordan Thimot, Kukjoo Kim, Chen Shi, Kenneth L Shepard
This paper describes an inductively powered 27-Mbps, 0.08-mm3 CMOS transceiver with integrated RF receiver coils for simultaneous two-way, near-field data telemetry and power transmission for implantable systems. A four-coil inductive link operates at a 27-MHz carrier for power and a 700-MHz carrier for data telemetry with the antennae taking an area of only 2 mm by 2 mm. Amplitude-shift-keying (ASK) modulation is used for data downlink at 6.6 kbps and load-shift keying (LSK) backscattering is used for data uplink at 27 Mbps. The transceiver consumes 2.7 mW and can power a load consuming up to an additional 1.5 mW. Implemented in a 0.18-um silicon-on-insulator (SOI) technology, post-processing steps are used to decrease chip thickness to approximately 15um, making the chip flexible with a tissue-like form factor and removing the effects of the substrate on coil performance. Power harvesting circuitry, including passive rectifier, voltage regulator, RF limiter, ASK and LSK modulator, clock generator, and digital controller are positioned adjacent to the coils and limited to an area of 0.5 mm by 2mm. Complete transceiver functionality of the system has been achieved with overall power transfer efficiency (PTE) of 1.04% through 1 mm of tissue phantom between reader and implant.
{"title":"A 27-Mbps, 0.08-mm<sup>3</sup> CMOS Transceiver with Simultaneous Near-field Power Transmission and Data Telemetry for Implantable Systems.","authors":"Jordan Thimot, Kukjoo Kim, Chen Shi, Kenneth L Shepard","doi":"10.1109/CICC48029.2020.9075888","DOIUrl":"https://doi.org/10.1109/CICC48029.2020.9075888","url":null,"abstract":"<p><p>This paper describes an inductively powered 27-Mbps, 0.08-mm<sup>3</sup> CMOS transceiver with integrated RF receiver coils for simultaneous two-way, near-field data telemetry and power transmission for implantable systems. A four-coil inductive link operates at a 27-MHz carrier for power and a 700-MHz carrier for data telemetry with the antennae taking an area of only 2 mm by 2 mm. Amplitude-shift-keying (ASK) modulation is used for data downlink at 6.6 kbps and load-shift keying (LSK) backscattering is used for data uplink at 27 Mbps. The transceiver consumes 2.7 mW and can power a load consuming up to an additional 1.5 mW. Implemented in a 0.18-um silicon-on-insulator (SOI) technology, post-processing steps are used to decrease chip thickness to approximately 15um, making the chip flexible with a tissue-like form factor and removing the effects of the substrate on coil performance. Power harvesting circuitry, including passive rectifier, voltage regulator, RF limiter, ASK and LSK modulator, clock generator, and digital controller are positioned adjacent to the coils and limited to an area of 0.5 mm by 2mm. Complete transceiver functionality of the system has been achieved with overall power transfer efficiency (PTE) of 1.04% through 1 mm of tissue phantom between reader and implant.</p>","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"2020 ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/CICC48029.2020.9075888","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"39219273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-03-01Epub Date: 2020-04-23DOI: 10.1109/cicc48029.2020.9075941
Hayden Bialek, Matthew L Johnston, Arun Natarajan
This work presents a technique for design of ultra-low power (ULP) CMOS voltage references achieving extremely low line sensitivity while maintaining state-of-the-art temperature insensitivity through the use of a 6-transistor (6T) structure. The proposed technique demonstrates good performance in sub-100 nm CMOS technologies. The 65-nm CMOS implementation occupies only 840 μm2 of area and consumes 28.6 pA from a 0.5 V supply. Measurements from 6 samples from the same wafer show an average line sensitivity of 0.02 %/V, a 10X improvement over previous 65 nm implementations, and an average temperature coefficient of 99.2 ppm/°C.
{"title":"A 6-Transistor Ultra-Low Power CMOS Voltage Reference with 0.02%/V Line Sensitivity.","authors":"Hayden Bialek, Matthew L Johnston, Arun Natarajan","doi":"10.1109/cicc48029.2020.9075941","DOIUrl":"https://doi.org/10.1109/cicc48029.2020.9075941","url":null,"abstract":"<p><p>This work presents a technique for design of ultra-low power (ULP) CMOS voltage references achieving extremely low line sensitivity while maintaining state-of-the-art temperature insensitivity through the use of a 6-transistor (6T) structure. The proposed technique demonstrates good performance in sub-100 nm CMOS technologies. The 65-nm CMOS implementation occupies only 840 <i>μ</i>m<sup>2</sup> of area and consumes 28.6 pA from a 0.5 V supply. Measurements from 6 samples from the same wafer show an average line sensitivity of 0.02 %/V, a 10X improvement over previous 65 nm implementations, and an average temperature coefficient of 99.2 ppm/°C.</p>","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"2020 ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/cicc48029.2020.9075941","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"38704288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510568
P. Klein, K. Hoffmann, O. Kowarik
The model allows the simulation of threshold voltage and drain current shifts as well as FN-tunnel and substrate currents caused by FN and band-to-band tunneling. This is achieved by determining the floating gate charge and voltage as function of time and short channel and geometry effects during programming, erasing and reading.
{"title":"An EEPROM compact circuit model","authors":"P. Klein, K. Hoffmann, O. Kowarik","doi":"10.1109/CICC.1996.510568","DOIUrl":"https://doi.org/10.1109/CICC.1996.510568","url":null,"abstract":"The model allows the simulation of threshold voltage and drain current shifts as well as FN-tunnel and substrate currents caused by FN and band-to-band tunneling. This is achieved by determining the floating gate charge and voltage as function of time and short channel and geometry effects during programming, erasing and reading.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"5 1","pages":"325-328"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81431451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510585
R. Mehra, L. Guerra, J. Rabney
We propose a new high-level synthesis technique for the low-power implementation of real-time applications. The technique uses algorithm partitioning to preserve locality in the assignment of operations to hardware units. This results in reduced usage of long high-capacitance buses, fewer accesses to multiplexers and buffers, and more compact layouts. Experimental results show average reductions in bus and multiplexer power of 62.9% and 38.5%, respectively, resulting in an average reduction of 18.5% in total power.
{"title":"Exploiting locality for low-power design","authors":"R. Mehra, L. Guerra, J. Rabney","doi":"10.1109/CICC.1996.510585","DOIUrl":"https://doi.org/10.1109/CICC.1996.510585","url":null,"abstract":"We propose a new high-level synthesis technique for the low-power implementation of real-time applications. The technique uses algorithm partitioning to preserve locality in the assignment of operations to hardware units. This results in reduced usage of long high-capacitance buses, fewer accesses to multiplexers and buffers, and more compact layouts. Experimental results show average reductions in bus and multiplexer power of 62.9% and 38.5%, respectively, resulting in an average reduction of 18.5% in total power.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"51 1","pages":"401-404"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84595228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510521
T. Burger, Qiuting Huang
A fully differential operational transconductance amplifier with a gain-bandwidth of 480 MHz at 52 degrees of phase margin and a DC-gain of 100 dB has been implemented in a 0.7 /spl mu/m CMOS process. The circuit utilizes the regulated cascode gain enhancement technique and has a switched-capacitor dynamic common mode feedback structure. It has been designed for a +/- 3 V output swing at a single supply of 5 V. The power consumption is 145 mW.
{"title":"A 100 dB, 480 MHz OTA in 0.7 /spl mu/m CMOS for sampled-data applications","authors":"T. Burger, Qiuting Huang","doi":"10.1109/CICC.1996.510521","DOIUrl":"https://doi.org/10.1109/CICC.1996.510521","url":null,"abstract":"A fully differential operational transconductance amplifier with a gain-bandwidth of 480 MHz at 52 degrees of phase margin and a DC-gain of 100 dB has been implemented in a 0.7 /spl mu/m CMOS process. The circuit utilizes the regulated cascode gain enhancement technique and has a switched-capacitor dynamic common mode feedback structure. It has been designed for a +/- 3 V output swing at a single supply of 5 V. The power consumption is 145 mW.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"2010 1","pages":"101-104"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86276705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510592
R. Telichevesky, K. Kundert, I. Elfadel, J. White
RF integrated circuit designers make extensive use of simulation tools which perform nonlinear periodic steady-state analysis and its extensions. However, the computational costs of these simulation tools have restricted users from examining the detailed behavior of complete RF subsystems. Recent algorithmic developments, based on matrix-implicit iterative methods, is rapidly changing this situation and providing new faster tools which can easily analyze circuits with hundreds of devices. In this paper we present these new methods by describing how they can be used to accelerate finite-difference, shooting-Newton, and harmonic-balance based algorithms for periodic steady-state analysis.
{"title":"Fast simulation algorithms for RF circuits","authors":"R. Telichevesky, K. Kundert, I. Elfadel, J. White","doi":"10.1109/CICC.1996.510592","DOIUrl":"https://doi.org/10.1109/CICC.1996.510592","url":null,"abstract":"RF integrated circuit designers make extensive use of simulation tools which perform nonlinear periodic steady-state analysis and its extensions. However, the computational costs of these simulation tools have restricted users from examining the detailed behavior of complete RF subsystems. Recent algorithmic developments, based on matrix-implicit iterative methods, is rapidly changing this situation and providing new faster tools which can easily analyze circuits with hundreds of devices. In this paper we present these new methods by describing how they can be used to accelerate finite-difference, shooting-Newton, and harmonic-balance based algorithms for periodic steady-state analysis.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"34 1","pages":"437-444"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83115691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510527
T. Stockstad, T. Petty, R. Yee
A rechargeable lithium battery safety IC designed for monitoring cell voltage and current in the battery is presented. The circuitry is capable of protecting batteries of one to four series connected cells via a programmable circuit architecture with a cell voltage limit accuracy of +/-1%. The circuitry has an average current drain of 25 /spl mu/A. The Li safety IC with integrated series FETs has an area of 18.4 mm/sup 2/.
{"title":"A micropower safety IC for rechargeable lithium batteries","authors":"T. Stockstad, T. Petty, R. Yee","doi":"10.1109/CICC.1996.510527","DOIUrl":"https://doi.org/10.1109/CICC.1996.510527","url":null,"abstract":"A rechargeable lithium battery safety IC designed for monitoring cell voltage and current in the battery is presented. The circuitry is capable of protecting batteries of one to four series connected cells via a programmable circuit architecture with a cell voltage limit accuracy of +/-1%. The circuitry has an average current drain of 25 /spl mu/A. The Li safety IC with integrated series FETs has an area of 18.4 mm/sup 2/.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"1 1","pages":"127-130"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80585635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510539
John R. Long, Miles A. Copeland
The results of a comprehensive investigation into the characteristics and optimization of inductors fabricated in the top-level metal of a sub-micron silicon VLSI process are presented. A computer program which extracts a physically-based model of microstrip components which is suitable for circuit (SPICE) simulation has been used to evaluate variations in metallization, layout geometry and substrate parameters upon inductor performance. 3-D numerical simulations and experimental measurements of inductors were also used to benchmark the model accuracy. It is shown in this work that low inductor Q is primarily due to the restrictions imposed by the thin interconnect metallization available in most VLSI technologies, and that computer optimization of the inductor layout can be used to achieve a 50% improvement in component Q-factor over unoptimized designs.
{"title":"Modeling, characterization and design of monolithic inductors for silicon RFICs","authors":"John R. Long, Miles A. Copeland","doi":"10.1109/CICC.1996.510539","DOIUrl":"https://doi.org/10.1109/CICC.1996.510539","url":null,"abstract":"The results of a comprehensive investigation into the characteristics and optimization of inductors fabricated in the top-level metal of a sub-micron silicon VLSI process are presented. A computer program which extracts a physically-based model of microstrip components which is suitable for circuit (SPICE) simulation has been used to evaluate variations in metallization, layout geometry and substrate parameters upon inductor performance. 3-D numerical simulations and experimental measurements of inductors were also used to benchmark the model accuracy. It is shown in this work that low inductor Q is primarily due to the restrictions imposed by the thin interconnect metallization available in most VLSI technologies, and that computer optimization of the inductor layout can be used to achieve a 50% improvement in component Q-factor over unoptimized designs.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"1 1","pages":"185-188"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89748891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510505
H. Heineken, J. Khare, Wojciech Maly
This paper describes three new yield models. The first takes as input the critical area of a layout; the second approximates the critical area with the minimum spacing area between metal lines; and the third uses transistor density to model critical area. The models were developed and verified using manufacturing data.
{"title":"Yield loss forecasting in the early phases of the VLSI design process","authors":"H. Heineken, J. Khare, Wojciech Maly","doi":"10.1109/CICC.1996.510505","DOIUrl":"https://doi.org/10.1109/CICC.1996.510505","url":null,"abstract":"This paper describes three new yield models. The first takes as input the critical area of a layout; the second approximates the critical area with the minimum spacing area between metal lines; and the third uses transistor density to model critical area. The models were developed and verified using manufacturing data.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"8 1","pages":"27-30"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87174250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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